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CLK
32 clock cycles
…
…
16 clock cycles
DATA
0x8D00
0
0
Figure 2-6. TWI_RST Command Timing Diagram
DATA
CLK
16 clock cycles
0x8D02 (TWI_OFF)
…
t
DD
Default
State
Figure 2-7. TWI_OFF Command Timing Diagram
DATA
CLK
16 clock cycles
0xBD01 (SOFT_RST)
…
t
DD
Default
State
Figure 2-8. SOFT_RST Command Timing Diagram
2.6
TWI Configuration Process
TWI configuration process is as follows:
TWI_RST
SOFT_RST
(wait 1 ms before moving to Step-3)
TWI_WRREG(0x02, 0x78)
(1) - TWI_WRREG(0x2F, 0x80)
(2) - TWI_WRREG(0x35, 0xCA)
(3) - TWI_WRREG(0x36, 0xEB)
(4) - TWI_WRREG(0x37, 0x37)
(5) - TWI_WRREG(0x38, 0x82)
(1) - TWI_WRREG(0x12, 0x10)
(2) - TWI_WRREG(0x12, 0x00)
(3) - TWI_WRREG(0x24, 0x07)
(4) - TWI_WRREG(0x1D, 0x20)
(1) - TWI_WRREG(0x18, Addr)
(2) - TWI_WRREG(0x19, Low_data)
(3) - TWI_WRREG(0x1A, High_data)
(4) - TWI_WRREG(0x25, 0x01)
TWI_OFF
TRANSMISSION
TWI_WRREG( 0x02, 0x7F)
1
2
3
3
4
5
6
6
7
8
Step-1
Step-2
Step-3
Step-4
Step-5
Step-7
Step-8
Step-9
Step-6
Figure 2-9. TWI Configuration Process Diagram
