
Evaluation Kit for CMX7x6x
PE0601-xxxx
©
2011 CML Microsystems Plc
5
UM0601/2
CMX7x6x
+V, J23
+3V3D
+4V0
J16
+V
Clocks
(19.2MHz
default)
SSP/GPIO, J7
Serial
Memory
C-BUS
Master,
J11
Instrumentation
Interface
I/Q_IN
I/Q_OUT
Supp
lies
Core
+3v3
Speaker
-4V0
-V
Auxiliary
ADC & DAC,
J13
RF
Interface,
J22
Audio
Inputs,
J1/2
Audio
Outputs,
J3/4
C-BUS &
Boot
Control, J10
+3V3A
Figure 1 – Block Diagram