Schematic Diagrams
B - 4 CPU 2/7 (CLK, MISC, JTAG)
B.Schematic Diagrams
CPU 2/7 (CLK, MISC, JTAG)
H _ P R O C H OT #
[ 3 6]
S
D
G
Q3 6 B
MT D N 7 0 02 Z H S 6 R
5
3
4
R 9 1
1 0 0 K _ 04
CLOC
KS
MI
SC
TH
ERMA
L
PW
R MAN
AGEM
ENT
DDR
3
MIS
C
J
TAG &
BP
M
U 3 4 B
P Z 98 8 2 7-3 6 4 B -0 1F
S M _ R C OMP [ 1]
A 5
S M _ R C OMP [ 2]
A 4
S M_ D R A MR S T #
R 8
S M _ R C OMP [ 0]
A K 1
B C L K #
A 27
B C LK
A 28
D P L L _ R E F _ S S C L K #
A 15
D P L L _R E F _ S S C LK
A 16
C A T E R R #
A L 3 3
P E C I
A N 3 3
P R O C H OT #
A L 3 2
TH E R M T R I P #
A N 3 2
S M_ D R A MP W R O K
V 8
R E S E T #
A R 3 3
P R D Y #
A P 2 9
P R E Q #
A P 2 7
T C K
A R 2 6
T MS
A R 2 7
TR S T #
A P 3 0
T D I
A R 2 8
T D O
A P 2 6
D B R #
A L3 5
B P M # [ 0]
A T2 8
B P M # [ 1]
A R 2 9
B P M # [ 2]
A R 3 0
B P M # [ 3]
A T3 0
B P M # [ 4]
A P 3 2
B P M # [ 5]
A R 3 1
B P M # [ 6]
A T3 1
B P M # [ 7]
A R 3 2
P M_ S Y N C
A M 3 4
S K T OC C #
A N 3 4
P R O C _ S E L E C T #
C 2 6
U N C OR E P W R GO OD
A P 3 3
C 2 2
0 . 0 47 u _ 10 V _ X 7R _ 04
R 5 9
0 _ 04
S3 circuit:- DRAM PWR GOOD logic
1 . 8 V S _ P W R G D
[ 1 5, 3 3 ]
P M_ D R A M_ P W R GD
[ 1 5]
P MS Y S _P W R G D _ B U F
R 7 3
*2 0 0_ 1 % _0 4
1 . 5 V _ C P U
R 57
1 0 K _ 04
R 58
* 39 _ 0 4
S U S B
[ 6 , 3 1, 3 3 , 3 4 ]
Q 10
* MT N 7 0 0 2Z H S 3
G
D
S
3 . 3V
11/0 3
S
D
G
Q3 6 A
MT D N 7 0 02 Z H S 6 R
2
6
1
R 5 3 0
1 0K _ 0 4
11/ 04
C 51 5
4 7 p_ 5 0 V _ N P O _0 4
H _ P R OC H OT #
R 9 0
* 0 _0 4
R 60
1 3 0_ 1 % _0 4
CAD Note: Capacitor
need to be placed
close to buffer output pin
H _ P R OC H O T_ E C
[ 2 7 ]
Q1 4
MT N 70 0 2 Z H S 3
G
D
S
C
A
A
D 2 0
*B A T5 4 A W G H
1
2
3
P M S Y S _ P W R GD _ B U F
R 41 4
5 1 _ 04
R 41 6
5 1 _ 04
R 10 8
5 1 _ 04
R 41 5
5 1 _ 04
R 10 9
* 51 _ 0 4
R 95
5 1 _ 04
3 . 3V S
1. 0 5 V S _ V T T
XD P _ D B R _R
R 40 7
1 K _ 0 4
XD P _ TM S
XD P _ TD O_ R
PU/PD for JTAG signals
XD P _ TR S T #
XD P _ P R E Q #
XD P _ TD I _ R
XD P _ TC L K
H _ C P U P W R GD _ R
R 10 6
*7 5 0_ 1 % _0 4
R 1 12
*1 . 5K _1 % _ 04
Processor Pullups/Pull downs
TRA CE W ID TH 1 0MI L, L EN GT H < 50 0M IL S
3 . 3 V S
B U F _C P U _ R S T#
DDR3 Compensation Signals
S M_ R C O MP _ 2
S M_ R C O MP _ 1
S M_ R C O MP _ 0
C 9 6
*6 8 p _5 0 V _ N P O _ 04
V D D P W R GO OD _ R
X D P _ T R S T #
X D P _ T C L K
P L T_ R S T #
[ 17 , 2 3 ]
X D P _ T MS
X D P _ T D I _ R
C P U D R A MR S T #
H _ P R OC H O T# _ D
H _ C A TE R R #
Buffered reset to CPU
X D P _ T D O _R
X D P _ P R E Q#
H _ T H R MT R I P #
[ 1 8 ]
H _S N B _ I V B #
[ 18 ]
R 38 2
2 5 . 5 _1 % _ 04
R 38 1
2 0 0_ 1 % _ 04
R 4 1 9
*1 0 mi l _ 04
R 41 2
10 K _ 0 4
R 41 3
1 4 0_ 1 % _ 04
H _ P E C I
[ 1 8 , 27 ]
P M_ S Y N C _R
If P RO CH OT # i s no t us ed, t he n it m ust
be t er mi na ted w it h a 68- O +- 5% p ul l-u p
re si st or t o 1 .0 5V S_ VT T .
Sandy Bridge Processor 2/7
( CLK,MISC,JTAG )
R 4 1 8
*1 0 mi l _ 04
R 41 0
62 _ 0 4
1 . 05 V S _ V T T
H _P R O C H O T #
S M _ R C OMP _2
S M _ R C OMP _0
S M _ R C OMP _1
C L K _ D P _ N [ 14 ]
C L K _ E XP _N
[ 1 4]
C L K _ E XP _P
[ 14 ]
H _ P M _S Y N C
[ 1 5 ]
C L K _ D P _ P [ 1 4 ]
H _ S N B _ I V B #
1 . 5V
[ 6 , 8 , 9, 1 0 , 2 0, 2 6 , 2 8 , 31 , 3 3 ]
1 . 5V _C P U
[ 6 , 3 1 ]
1 . 05 V S _ V T T
[ 2 , 5 , 1 8, 1 9 , 2 0 , 34 , 3 6 ]
3 . 3V
[ 2, 8 , 1 1 , 13 , 1 4 , 1 5, 1 7 , 1 8, 19 , 2 0 , 22 , 2 3 , 2 6, 2 8 , 3 0, 3 1 , 3 3 , 34 , 3 5 ]
H _ C P U P W R G D
[ 1 8]
Q8
MT N 70 0 2 Z H S 3
G
D
S
R 4 6
4
.99
K
_
1%
_04
C P U D R A M R S T #
R 4 7
*0 _0 4
1 . 5V
R 4 5
1K _ 0 4
S3 circuit:- DRAM_RST# to memory
should be high during S3
D R A M R S T _ C N TR L [ 8 , 14 ]
D D R 3_ D R A M R S T # [ 9 , 10 ]
R 48
1K _0 4
10/1
X D P _ D B R _ R
R 4 1 1
*1 0 mi l _ 04
X D P _ B P M 1_ R
X D P _ B P M 0_ R
X D P _ B P M 6_ R
X D P _ B P M 5_ R
X D P _ B P M 4_ R
X D P _ B P M 3_ R
X D P _ B P M 2_ R
X D P _ B P M 7_ R
H _ P E C I _ R
R 1 0 5
7 5_ 1 % _0 4
R 4 0 5
5 6 _1 % _ 04
H _C P U P W R G D _ R
R 1 04
43 _ 1 %_ 0 4
10 /2 9
R 5 3 1
1 00 K _ 0 4
C 58 5
* 0. 1 u _ 10 V _ X 7 R _ 0 4
X D P _ P R D Y #
10/28
1 . 0 5 V S _ V T T
3 . 3V S
[ 9, 1 0 , 1 1 , 12 , 1 3 , 14 , 1 5 , 1 6, 1 7 , 1 8, 19 , 2 0 , 23 , 2 4 , 2 5, 2 7 , 2 8, 2 9 , 3 0 , 31 , 3 6 ]
R 4 1 7
*1 0 mi l _ 04
H _ T H R MT R I P #_ R
Sheet 3 of 43
CPU 2/7
(CLK, MISC, JTAG)
Summary of Contents for W270HUQ Series
Page 1: ...W270HUQ Series ...
Page 2: ......
Page 3: ...Preface I Preface Notebook Computer W270HUQ Service Manual ...
Page 24: ...Introduction 1 12 1 Introduction ...
Page 42: ...Disassembly 2 18 2 Disassembly ...
Page 45: ...Top A 3 A Part Lists Top 灰 色 Figure A 1 Top ...
Page 46: ...A 4 Bottom A Part Lists Bottom Figure A 2 Bottom ...
Page 47: ...SATA BLU RAY COMBO A 5 A Part Lists SATA BLU RAY COMBO 志精 Figure 3 SATA BLU RAY COMBO ...
Page 48: ...A 6 SATA DVD DUAL A Part Lists SATA DVD DUAL Figure 4 SATA DVD DUAL 志精 ...
Page 49: ...LCD A 7 A Part Lists LCD Figure A 5 LCD ...
Page 50: ...A 8 LCD A Part Lists ...
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