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SPA 0 table:
=======================================
SPA OIR state
: present
SPA state
: enabled
SPA allocated Rx buffer size
: 4MB
SPA available Rx buffer size
: 0x20c000
RxSPI PLL reset
: inactive
Header Format type
: Format A
Pad bytes
: 0
L2LA
: 0
Strict priority mode
: active
EFC Manager
: disabled
SPA dual wide mode
: inactive
Max SPA channels
: 10
PLIM loopback
: inactive
SPI loopback
: inactive
DatamaxT
: 4096
Training M
: 16
DIP2 Match
: 3
DIP2 Error
: 3
Tx SClk edge
: falling
DIP4 Match
: 15
DIP4 Error
: 2
Rx SClk edge
: rising
SPI bus speed
: 350MHz
Tx Burst size
: 64 Bytes
Rx Burst size sysdb
: 80 Bytes
Rx SPI state
: enabled
Rx SPI sync state
: inframe
Rx calendar mode
: single
Maximun RxSPI channels
: 10
Tx SPI state
: enabled
Tx SPI sync state
: inframe
Tx calendar mode
: single
Maximun Tx SPI4.2 channels
: 5
This table describes the significant fields shown in the display.
Table 4: show controllers plim asic spa bay Field Descriptions
Description
Field
Current OIR
status for this SPA.
SPA OIR state
Current state of the specified SPA. Can be enabled
or disabled.
SPA state
Number of bytes allocated for the receive buffer.
SPA allocated Rx buffer size
Number of bytes available in the receive buffer.
SPA available Rx buffer size
SPI PLL receive timer reset value.
RxSPI PLL reset
Header format used by this ASIC.
Header Format type
Number of pad bytes allowed to fill out the packets
sent on this ASIC.
Pad bytes
Layer 2 Length Adjust. When a length entry has been
read or is being written, this bit contains the value of
the L2LA field.
L2LA
Cisco IOS XR Advanced System Command Reference for the Cisco XR 12000 Router, Release 5.1.x
OL-30353-01
11
ASIC Driver Commands
show controllers plim asic spa bay