Cirrus Logic CS8952 Manual Download

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CS8952

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

10BASE-T MII TRANSMIT TIMING

Parameter

Symbol

Min

Typ

Max

Unit

TXD[3:0] Setup to TX_CLK High

SU1

TX_ER Setup to TX_CLK High

SU2

TX_EN Setup to TX_CLK High

SU3

TXD[3:0] Hold after TX_CLK High

HD1

TX_ER Hold after TX_CLK High

HD2

TX_EN Hold after TX_CLK High

HD3

TX_EN “high” to CRS asserted latency

CRS1

TX_EN “low” to CRS de-asserted latency

CRS2

TX_EN “high” to TX+/- output (TX Latency)

LAT

SQE Timing

COL (SQE) Delay after CRS de-asserted

COL

0.65

0.9

1.6

COL (SQE) Pulse Duration

COLP

0.65

1.0

1.6

TX_CLK

TX_EN

TX_ER

TXD[3:0]

CRS

TX+/-

SU3

SU2

SU1

HD3

HD2

HD1

CRS1

CRS2

LAT

Valid

Data

Input/Output

Input

Output

TX_CLK

SQE

COL

SQEP

Input/Output

Output

SQE Timing

10BASE-T Transmit Timing

Summary of Contents for CS8952

Page 1: ... optimized for noise and near end crosstalk NEXT immunity to extend receiver operation to cable lengths exceeding 160 m In addition the transmit cir cuitry has been designed to provide extremely low transmit jitter 400 ps for improved link partner perfor mance Transmit driver common mode noise has been minimized to reduce EMI for simplified FCC certification The CS8952 incorporates a standard Medi...

Page 2: ...sure that the information contained in this document is accurate and reliable However the information is subject to change without notice and is provided AS IS without warranty of any kind express or implied Customers are advised to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subjec...

Page 3: ...uto Negotiation Expansion Register Address 06h 40 Auto Negotiation Next Page Transmit Register Address 07h 41 Interrupt Mask Register Address 10h 42 Interrupt Status Register Address 11h 45 Disconnect Count Register Address 12h 48 False Carrier Count Register Address 13h 49 Scrambler Key Initialization Register Address 14h 50 Receive Error Count Register Address 15h 51 Descrambler Key Initializati...

Page 4: ...eet the fol lowing specifications Parameter Symbol Min Max Unit Power Supply VDD VDD_MII 0 3 0 3 6 0 6 0 V Input Current Except Supply Pins 10 0 mA Input Voltage 0 3 VDD 0 3 V Ambient Temperature Power Applied 55 125 C Storage Temperature 65 150 C Parameter Symbol Min Max Unit Power Supply Core MII VDD VDD_MII 4 75 3 0 5 25 5 25 V V Operating Ambient Temperature TA 0 70 C Parameter Min Typ Max Uni...

Page 5: ...ASE FX Note 1 10BASE T Note 1 IDD 135 90 80 145 mA Hardware Power Down Note 1 IDDHPDN 900 µA Software Power Down Note 1 IDDSPDN 20 mA Low Power Power Up Note 1 IDDSLPUP 900 µA Digital I O Output Low Voltage CLK25 MII_IRQ SPD10 SPD100 IOL 4 0mA LED 4 0 IOL 10 0mA VOL 0 4 0 4 V Output Low Voltage MII_DRV 1 COL CRS MDIO RXD 3 0 RX_CLK RX_DV RX_ER TX_CLK IOL 4 0mA VDD_MII 5V IOL 43 0mA VDD_MII 3 3V IO...

Page 6: ...nputs Except AN 1 0 TCM TXSLEW 1 0 VIH 2 0 V Tri Level Input Voltages AN 1 0 TCM TXSLEW 1 0 VIL VIM VIH 1 3 VDD_MII 20 2 3 VDD_MII 20 1 3 VDD_MII 20 2 3 VDD_MII 20 V Input Low Current MDC TXD 3 0 TX_CLK TX_EN TX_ER VI 0 0V MDIO VI 0 0V IIL 20 3800 µA Input High Current MDC TXD 3 0 TX_CLK TX_EN TX_ER VI 5 0V MDIO VI 5 0V IIH 200 20 µA Input Leakage Current All Other Inputs 0 V VDD ILEAK 10 10 µA DC...

Page 7: ...eiver Allowable Received Jitter at Bit Cell Center tTRX1 13 5 ns Allowable Received Jitter at Bit Cell Boundary tTRX2 13 5 ns 10BASE T Link Integrity First Transmitted Link Pulse after Last Transmit ted Packet tLN1 15 16 17 ms Time Between Transmitted Link Pulses tLN2 15 16 17 ms Width of Transmitted Link Pulses tLN3 60 200 ns Minimum Received Link Pulses Separation tLN4 2 5 7 ms Maximum Received ...

Page 8: ...ifferential Output Impedance ZOUT 100 ohms 100BASE TX Receiver Receive Signal Detect Assert Threshold 1 0 Vp p Receive Signal Detect De assert Threshold 0 2 Vp p Receive Signal Detect Assert Time 1000 µs Receive Signal Detect De assert Time 350 µs 100BASE FX Transmitter TX_NRZ Output Voltage Low V1 1 830 1 605 V TX_NRZ Output Voltage High V2 1 035 0 880 V Signal Rise Fall Time TRF 1 6 ns 100Base F...

Page 9: ...o RXD latency 4B Aligned 5B Aligned tDLAT 2 2 3 6 3 6 8 8 BT Start of Stream to CRS asserted tCRS1 10 11 BT End of Stream to CRS de asserted tCRS2 21 BT Start of Stream to COL asserted tCOL1 11 BT End of Stream to COL de asserted tCOL2 21 BT RX_EN asserted to RX_DV RXD 3 0 valid tEN TBD ns RX_EN de asserted to RX_DV RXD 3 0 RX_ER RXD4 in high impedance state tDIS TBD ns RX_CLK RXD 3 0 CRS tCRS1 tC...

Page 10: ...nit RX_CLK Period tP 40 ns RX_CLK Pulse Width tWL tWH 20 ns RXD 4 0 setup to rising edge of RX_CLK tSU 10 ns RXD 4 0 hold after rising edge of RX_CLK tHD 10 ns Start of 5B symbol to symbol output on RX 4 0 5B Mode tRLAT 5 9 BT RX_CLK RXD 4 0 tRLAT RX Symbol 0 RX Symbol N RX IN OUT OUT tHD tWL tWH tP tSU RX Symbol N 1 RX Data 0 RX Data 1 ...

Page 11: ... tSU2 10 ns TXD 3 0 Hold after TX_CLK High tHD1 0 ns TX_ER Hold after TX_CLK High tHD2 0 ns TX_EN Hold after TX_CLK High tHD3 0 ns TX_EN high to CRS asserted latency tCRS1 8 BT TX_EN low to CRS de asserted latency tCRS2 8 BT TX_EN high to TX output TX Latency tLAT 6 7 8 BT TX_CLK TX_EN TXD 3 0 CRS TX tSU2 tSU1 tHD2 tHD1 tCRS1 tCRS2 tLAT Input Output Input Input Output Output TX_ER TXD4 Data IN Sym...

Page 12: ...S ALIGN MODE Parameter Symbol Min Typ Max Unit TXD 4 0 Setup to TX_CLK High tSU1 10 ns TXD 4 0 Hold after TX_CLK High tHD1 0 ns TX_ER Hold after TX_CLK High tHD2 0 ns TXD 4 0 Sampled to TX output TX Latency tLAT 6 7 ns TX_CLK TXD 4 0 TX tSU1 tHD1 tLAT Symbol OUT Input Output Input Output Data IN ...

Page 13: ...LK tHD 30 ns RX data valid from CRS tRLAT 8 10 BT RX preamble to CRS asserted tCRS1 5 7 BT RX end of packet to CRS de asserted tCRS2 2 5 3 BT RX preamble to COL asserted tCOL1 0 7 BT RX end of packet to COL de asserted tCOL2 3 BT RX_EN asserted to RX_DV RXD 3 0 RX_ER valid tEN 60 ns RX_EN de asserted to RX_DV RXD 3 0 RX_ER in high impedance state tDIS 60 ns RX_CLK RXD 3 0 CRS tCRS1 tCOL2 tRLAT RX_...

Page 14: ...s TX_EN Hold after TX_CLK High tHD3 0 ns TX_EN high to CRS asserted latency tCRS1 0 4 BT TX_EN low to CRS de asserted latency tCRS2 0 16 BT TX_EN high to TX output TX Latency tLAT 6 14 BT SQE Timing COL SQE Delay after CRS de asserted tCOL 0 65 0 9 1 6 µs COL SQE Pulse Duration tCOLP 0 65 1 0 1 6 µs TX_CLK TX_EN TX_ER TXD 3 0 CRS TX tSU3 tSU2 tSU1 tHD3 tHD2 tHD1 tCRS1 tCRS2 tLAT Valid Data Input O...

Page 15: ...t RX active to RXD 0 active tDATA 1200 ns RX active to CRS active tCRS 600 ns RXD 0 setup from RX_CLK tRDS 35 ns RXD 0 hold from RX_CLK tRDH 50 ns RX_CLK hold after CRS off tRCH 5 ns RXD 0 throughput delay tRD 250 ns CRS turn off delay tCRSOFF 400 ns RX_CLK RXD 0 CRS tCRS RX IN OUT OUT tCRSOFF tHD tSU OUT tDATA tRD tRCH ...

Page 16: ...t TX_EN Setup from TX_CLK tEHCH 10 ns TX_EN Hold after TX_CLK tCHEL 10 ns TXD 0 Setup from TX_CLK tDSCH 10 ns TXD 0 Hold after TX_CLK tCHDU 10 ns Transmit start up delay tSTUD 500 ns Transmit throughput delay tTPD 500 ns TX_CLK TX_EN TXD 3 0 TX tEHCH tDSCH tCHEL tCHDU tSTUD Valid Data Input Output Input Input Output tPD ...

Page 17: ...n Typ Max Unit FLP burst to FLP burst tBTB 15 16 17 ms FLP burst width tFLPW 2 ms Clock Data pulses per burst 17 33 ea Clock Data pulse width tPW 100 ns Clock pulse to Data pulse tCTD 55 5 64 69 5 µs Clock pulse to clock pulse tCTC 111 128 139 µs tFLPW tBTB Clock Pulse Data Pulse Clock Pulse tPW tCTD tCTC tPW TX TX ...

Page 18: ...mbol Min Typ Max Unit MDC Period tp 60 ns MDC Pulse Width tWL tWH 40 60 MDIO Setup to MDC MDIO as input tMD1 10 ns MDIO Hold after MDC MDIO as input tMD2 10 ns MDC to MDIO valid MDIO as output tMD3 0 40 ns MDC MDIO MDIO Valid Data DIRECTION IN or OUT of chip IN IN OUT tMD1 tMD2 tMD3 Valid Data Valid Data ...

Page 19: ...ustrates a typical MII to CS8952 appli cation with twisted pair and fiber interfaces Refer to the Analog Design Considerations section for detailed information on power supply requirements and decoupling crystal and magnetics require ments and twisted pair and fiber transceiver con nections 3 FUNCTIONAL DESCRIPTION The CS8952 is a complete physical layer transceiv er for 100BASE TX and 10BASE T ap...

Page 20: ...ST0 TEST1 7 21 0 1 µF 0 1 µF 51 Ω 51 Ω 8 7 51 Ω 6 5 51 Ω 4 3 2 1 51 Ω 51 Ω 75 Ω 75 Ω 0 01 µF 2KV SHLD SHLD RJ45 RX RX TX TX 130 Ω 191 Ω 82 Ω 68 Ω 0 1 µF 63 4 Ω 82 Ω 82 Ω 5 V 5 V 0 1 µF 0 1 µF 49 9 Ω 49 9 Ω 130 Ω 130 Ω SD TD TD VCC VCC RD RD VEE VEE FIBER TRANSCEIVER SIGNAL SIGNAL TX_NRZ TX_NRZ RX_NRZ RX_NRZ AN0 AN1 NC NC CS8952 RX_EN PWRDN REPEATER BPSCR BP4B5B BPALIGN LPBK ISODEF 10BT_SER RESET M...

Page 21: ...SE X MII Application TX and FX The CS8952 provides an IEEE 802 3 compliant MII interface Data is transferred across the MII in four bit parallel nibble mode TX_CLK and RX_CLK are nominally 25 MHz for 100BASE X The 100BASE X mode includes both the TX and FX modes as determined by pin BPSCR bypass scrambler or the BPSCR bit bit 13 in the Loop back Bypass and Receiver Error Mask Register address 18h ...

Page 22: ...X_EN They are not generated through any combination of TXD 3 0 or TX_ER 3 IDLE is indicated by RX_DV 0 Code Violations RX_ER 1 or TX_ER 1 Name 5 bit Symbol Normal Mode 4 bit Nibble Error Report Mode 4 bit Nibble Comments CONTROL Note 1 I 11111 0000 0000 This portion of the table relates received 5 bit symbols to received 4 bit nibbles only The control code groups may not be transmitted in the data...

Page 23: ... In repeater mode pin RX_ER is rede fined as the fifth receive data bit RXD4 and pin TX_ER is redefined as the fifth transmit data bit TXD4 BPALIGN can also be selected by setting bit 12 in Loopback Bypass and Receiver Error Mask Reg ister address 18h BP4B5B can be selected by set ting bit 14 of the same register Pin BPALIGN causes more of the CS8952 to be bypassed than the BP4B5B pin BPALIGN also...

Page 24: ...ion If no receive activity is detected the CS8952 disables packet transmission to prevent blind transmis sions onto the network link pulses are still sent while packet transmission is disabled To reactivate transmission the receiver must detect a single pack et the packet itself is ignored or two normal link pulses separated by more than 6 ms and no more than 50 ms The CS8952 automatically checks ...

Page 25: ...ly on pins RXD0 and TXD0 using a 10 MHz RX_CLK and TX_CLK Receive data is framed by CRS rather than RX_DV 3 2 Auto Negotiation The CS8952 supports auto negotiation which is the mechanism that allows the two devices on ei ther end of an Ethernet link segment to share infor mation and automatically configure both devices for maximum performance When configured for auto negotiation the CS8952 will de...

Page 26: ...952 enters or exits the power down state as requested by pin PWRDN 6 Analog circuitry is reset and recalibrated when ever the CS8952 changes between 10 Mb s and 100 Mb s modes After a reset the CS8952 latches the signals on var ious input pins in order to initialize key registers and goes through a self configuration This in cludes calibrating on chip analog circuitry Time required for the reset c...

Page 27: ...rate only the nominal clock frequency is changed 4 1 MII Frame Structure Data frames transmitted through the MII have the following format Each frame is preceded by an inter frame gap The inter frame gap is an unspecified time during which no data activity occurs on the media as indi cated by the de assertion of CRS for the receive path and TX_EN for the transmit path The Preamble consists of seve...

Page 28: ...ycle after the last nibble of data CRC has been presented to the CS8952 When TX_EN is not as serted data on TXD 3 0 is ignored Transmit errors should be signaled by the MAC by asserting TX_ER for one or more TX_CLK cycles TX_ER must be synchronous with TX_CLK This will cause the CS8952 to replace the nibble with a HALT symbol in the frame being transmitted This invalid data will be detected by the...

Page 29: ... keep MDIO pulled to a logic ONE At the beginning of each transaction the MAC will typically send a sequence of 32 contiguous logic ONE bits on MDIO with 32 corresponding clock cycles on MDC to provide the CS8952 with a pat tern that it can use to establish synchronization Optionally the CS8952 may be configured to oper ate without the preamble through bit 9 of the PCS Sub Layer Configuration Regi...

Page 30: ...t times via individual control lines Some configuration capabilities are available at any time via individual control lines 5 1 Configuration At Power up Reset Time At power up and reset time the following pins are 5 2 Configuration Via Control Pins The following pins are for dedicated control signals and can be used at any time to configure the CS8952 5 3 Configuration via the MII The CS8952 supp...

Page 31: ...sk Register Read Write 11h Interrupt Status Register Read Only 12h Disconnect Count Register Read Only 13h False Carrier Count Register Read Only 14h Scrambler Key Initialization Register Read Write 15h Receive Error Count Register Read Only 16h Descrambler Key Initialization Register Read Write 17h PCS Sub Layer Configuration Register Read Write 18h Loopback Bypass and Receiver Error Mask Registe...

Page 32: ...s enabled via the AN 1 0 pins reset to 1 otherwise reset to 0 When bit 12 is clear setting this bit configures the CS8952 for 100 Mb s operation Clearing this bit sets the configuration at 10 Mb s When bit 12 is set this bit is ignored 12 Auto Neg Enable Read Write If auto negotiation is enabled via the AN 1 0 pins reset to 1 otherwise reset to 0 Setting this bit enables the auto negotiation proce...

Page 33: ...ear this bit controls the Full Duplex Half Duplex operation of the part When set the part is configured for Full Duplex operation and when clear the part is configured for Half Duplex operation The setting of this bit is superseded by auto negotiation and thus has no effect if bit 12 is set 7 Collision Test R W 0 When set the COL pin will be asserted within 10 bit times in response to the assertio...

Page 34: ...0BASE T Full Duplex bit in the Auto Negotiation Advertisement Register address 04h 11 10BASE T Half Duplex Read Only 1 When this bit is set it indicates that the CS8952 is capable of 10BASE T Half Duplex operation This bit reflects the status of the 10BASE T Half Duplex bit in the Auto Negotiation Advertisement Register address 04h 10 7 Reserved Read Only 0000 6 MF Preamble Sup pression Read Only ...

Page 35: ...longer than 105 ms then the packet output is terminated by the jabber logic and this bit is set If JabberiE Inter rupt Mask Register address 10h bit 3 is set an MII Interrupt will be generated This bit is implemented with a latching function so that the occurrence of a jabber condition causes it to become set until it is cleared by a read to this regis ter a read to the Interrupt Status Register a...

Page 36: ...e 001Ah This identifier is assigned to PHY manufacturers by the IEEE Its intention is to provide sufficient informa tion to support 10 100 Management as defined in Clause 30 1 2 of the IEEE 802 3 specification This register contains bits 3 18 of the OUI Bit 3 of the OUI is located in bit 15 of the PHY Identifier bit 4 of the OUI is in bit 14 and so on Note This field is disabled and writes to this...

Page 37: ... is located in bit 15 of this register bit 20 of the OUI is in bit 14 and so on Note This field is disabled and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE T Configuration Register address 1Ch is set 9 4 Part Number Read Write 10 0000 These bits indicate the CS8952 part number It has been set to a value of 100000 Note This field is disabled and writes to t...

Page 38: ...ion of the link partner s data 13 Remote Fault Read Write 0 This bit may be used to indicate a fault condition to the link partner Setting this bit will signal to the link partner that a fault condition has occurred 12 5 Technology Ability Field Read Write 0000 1111 This field determines the advertised capabilities of the CS8952 as shown below When the bit is set the corresponding technology will ...

Page 39: ...is bit indicates that a fault condition occurred on the far end When this bit is set and auto negotiation is enabled the Remote Fault bit in the Basic Mode Status Register address 01h will also be set 12 5 Technology Ability Field Read Only 0000 0000 This field indicates the advertised capabilities of the link partner as shown below When the bit is set the corresponding technology has been adverti...

Page 40: ...tner Next Page Able Read Only 0 When set this bit indicates that the link partner is capable of Next Page exchange 2 Next Page Able Read Only 1 This bit is a status bit which indicates to the Manage ment Layer that the CS8952 supports Next Page capability Note This bit is disabled and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE T Configuration Register add...

Page 41: ...ates that the data in the Mes sage Unformatted Code Field is one of the pre defined message pages When low the data is unformatted data Note This bit is disabled and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE T Configuration Register address 1Ch is set 12 Acknowledge 2 Read Write 0 When set this bit indicates to the link partner that the CS8952 can comply...

Page 42: ...function Note This bit is disabled and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE T Configuration Register address 1Ch is set 14 Link Status Change Read Write 1 When set an interrupt will be generated each time the CS8952 detects a change in the link status Note This bit is disabled and writes to this bit are ignored when the National Compatibility Mode b...

Page 43: ...n Register address 1Ch is set 8 Remote Loopback Fault Read Write 0 When set an interrupt will be generated if the elastic buffer in the PMA is under run or over run during Remote Loopback This should not occur for normal length 802 3 frames Note This bit is disabled and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE T Configuration Register address 1Ch is set...

Page 44: ...paral lel detection has occurred for a technology that is not currently advertised by the local device Note This bit is disabled and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE T Configuration Register address 1Ch is set 2 Remote Fault Read Write 0 When set an interrupt will be generated if a remote fault condition is detected either by auto negotiation or...

Page 45: ...link 13 Descrambler Lock Change Read Only 0 When set this bit indicates that a change has occurred in the status of the descrambler The Self Status Register address 19h may be read to deter mine the current status of the scrambler lock 12 Premature End Error Read Only 0 This bit is set when a premature end of frame is detected for 100 Mb s operation A premature end is defined as two consecutive ID...

Page 46: ...condition causes it to become set until it is cleared by a read to this regis ter a read to the Basic Mode Status Register address 01h or a reset No jabber detect function has been defined for 100BASE TX This bit is the same as in the Basic Mode Status Reg ister address 01h 5 Auto Neg Complete Read Only 0 This bit is set when the auto negotiation process has completed This is an indication that th...

Page 47: ...e set when the Far End Fault Indication for 100BASE TX is detected 1 Page Received Read Only 0 When set this bit indicates that a valid word of auto negotiation data has been received and its integrity verified The first page of data will consist of the Base Page and all successive pages will consist of Next Page data This bit is self clearing This bit is the same as in the Auto Negotiation Expans...

Page 48: ... 14 13 12 11 10 9 8 Disconnect Counter 7 6 5 4 3 2 1 0 Disconnect Counter BIT NAME TYPE RESET DESCRIPTION 15 0 Disconnect Counter Read Write 0000h This field contains a count of the number of times the CS8952 has lost a Link OK condition This counter is cleared upon readout and will roll over to 0000h ...

Page 49: ...BIT NAME TYPE RESET DESCRIPTION 15 0 False Carrier Counter Read Only 0000h This field contains a count of the number of times the CS8952 has detected a false carrier that is the reception of a poorly formed Start of Stream Delim iter SSD The counter is incremented at the end of such events to prevent multiple increments This counter is cleared upon readout and will saturate at FFFFh ...

Page 50: ...d Only 0000 These bits should be read as don t cares and when written should be written to 0 10 0 Scrambler Initializa tion Key Read Write Reset value is dependent on the PHY Address field of the Self Status Register address 19h This field allows the Scrambler to be loaded with a user definable key sequence A value of 000h has the effect of bypassing the scrambler function This is valuable for tes...

Page 51: ... Receive Error Counter 7 6 5 4 3 2 1 0 Receive Error Counter BIT NAME TYPE RESET DESCRIPTION 15 0 Receive Error Counter Read Only 0000h This counter increments for each packet in which one or more receive errors is detected that is not due to a collision event This counter is cleared upon readout and will roll over to 0000h ...

Page 52: ...d Only 0000 These bits should be read as don t cares and when written should be written to 0 10 0 Descrambler Initial ization Key Read Write Reset value is dependent on the PHY Address field of the Self Status Register address 19h This register allows the Descrambler to be loaded with a user definable key sequence A value of 000h has the effect of bypassing the descrambler function This is valuabl...

Page 53: ...e receive descrambler is disabled When this bit is clear the time out counter is enabled 12 Repeater Mode Read Write Reset to the value on the REPEATER pin This bit defines the mode of the Carrier Sense CRS signal When this bit is set CRS is asserted due to receive activity only When this bit is clear CRS is asserted due to either transmit or receive activity 11 LED5 Mode Read Write 0 This bit def...

Page 54: ...M pin is low reset to 1 otherwise reset to 0 Setting this bit will disable tri state the CLK25 out put pin reducing digital noise and power consump tion 6 Enable LT 100 Read Write 1 When set normal link status checking is enabled When clear this bit forces the link status to Link OK at 100 Mb s and will assert the LINK_OK LED 5 CIM Disable Read Write Reset to the logic inverse of the value on the ...

Page 55: ...it of the 10BASE T Configuration Register address 1Ch is set 2 LED1 Mode Read Write 0 This bit defines the mode of Pin LED1 When this bit is set pin LED1 indicates Carrier Integrity Monitor status as determined by the CIM Status bit in the Self Status Register address 19h When this bit is clear LED1 indicates 10 Mb s or 100 Mb s transmission activity 1 LED4 Mode Read Write 0 This bit defines the m...

Page 56: ... be bypassed 13 Bypass Scrambler Read Write Reset to the value on the BPSCR pin When set this bit causes the receive descrambler and the transmit scrambler blocks to be bypassed and the CS8952 accepts NRZI data from an external 100BASE FX optical module through pins RX_NRZ and RX_NRZ 12 Bypass Symbol Alignment Read Write Reset to the value on the BPALIGN pin When set this bit causes the following ...

Page 57: ...e of operation When set CRS will be asserted for transmit data only When clear CRS will be asserted only for receive data 5 Loopback Transmit Disable Read Write 1 This bit controls whether loopback data is transmitted onto the network When set any data transmitted during PMD or ENDEC loopback mode will NOT be transmitted onto the network When clear data will be transmitted on the TX pins as well a...

Page 58: ...on RXD 3 0 and the asser tion of RX_ER When clear packet errors are not reported across the MII 0 Code Error Report Enable Read Write 0 When set code errors are reported and transmitted on RXD 3 0 When clear this bit enables the Code Error Report values on RXD 3 0 as selected by the Code Error Report Select bit and also causes the assertion of TX_ER to transmit a HALT code group Note This bit is d...

Page 59: ... on the REPEATER pin This bit controls the state of the CRS pin upon a descrambler time out When set CRS will be forced low upon a descrambler time out and will not be released until the descrambler has re acquired syn chronization 10 Auto Neg Enable Status Read Only If auto negotiation is enabled via the AN 1 0 pins reset to 1 otherwise reset to 0 This bit reflects the value of bit 12 in the Basi...

Page 60: ...s 17h is clear this bit is set and latched It will remain set until this register is read 4 0 PHY Address Field Read Write Reset to the val ues on the PHYAD 4 0 pins The value on pins PHYAD 4 0 are latched into this field at power up or reset These bits define the PHY address used by the management layer to address the PHY The external logic must know this address in order to select this particula...

Page 61: ...clear the polarity is reversed If the Polarity Disable bit of 10BASE T Configuration Register address 1Ch is clear then the polarity is automatically corrected if needed The Polarity OK status bit shows the true state of the incoming polarity independent of the Polarity Disable bit 9 10BASE T Serial Read Write Reset to the value on the 10BT_SER pin When set this bit selects 10BASE T serial mode Wh...

Page 62: ...eration with auto negotiation enabled the CS8952 will go into 10 Mb s mode If operating in 100 Mb s mode with no auto negotiation then clear ing this bit has no effect 4 SQE Enable Read Write Reset to the logic inverse of the value on the REPEATER pin When set and if the CS8952 is in half duplex mode this bit enables the 10BASE T SQE function When the part is in repeater mode this bit is cleared a...

Page 63: ...is used recommended the shield should be connect ed to chassis ground 7 2 100BASE FX Interface Figure 7 shows the recommended connection for a 100BASE FX interface to a Hewlett Packard HFBR 5103 fiber transceiver Termination circuit ry may need to be revised for other fiber transceiv ers The FX Drive bit in the Loopback Bypass and Receiver Error Mask Register address 18h may be used to tailor the ...

Page 64: ... and should be placed as close as possible to RES pin Connect the other end of this resistor directly to the ground plane Connect the adjacent CS8952 ground pins pins 85 and 87 to the grounded end of the resistor forming a shield around the RES con nection 7 4 Clocking Schemes The CS8952 may be clocked using one of three possible schemes using a 25 MHz crystal and the internal oscillator using an ...

Page 65: ...als Table 7 lists examples of manufacturers with transformers meeting these requirements However the designer should evaluate the magnet ics for suitability in their specific design 7 6 Power Supply and Decoupling The CS8952 supports connection to either a 3 3 V or 5 0 V MII When connected to a 5 0 V MII all power pins should be provided 5 0 V 5 and all signal inputs should be referenced to 5 0V W...

Page 66: ...l signals TX RX TX_NRZ and RX_NRZ These should be run as microstrip transmission lines 100 Ωdifferential 50 Ωsin gle ended The MII signals should be 68 Ωmi crostrip transmission lines For short MII signal paths one may standardize on a given trace width for all traces without significant degradation in signal integrity Avoid routing traces other than the TX and RX signals under transformer T1 and ...

Page 67: ...ons close to the load Thus the TX_NRZ termination com ponents must be kept close to the fiber optic transceiver and the RX_NRZ and SIG NAL termination components must be kept close to the CS8952 Locate the crystal as close to the CS8952 as possible running short traces on the component side in order to reduce parasitic load capaci tance Add bulk capacitance at each connector where power may be sup...

Page 68: ...AD3 RXD2 RXD1 PHYAD1 RXD0 RX_DV MII_DRV VDD_MII VSS RX_CLK RX_ER RXD4 PHYAD4 TX_ER TXD4 VSS VDD VSS TX_CLK TX_EN TXD0 TXD1 TXD2 TXD3 COL PHYAD0 CRS PHYAD2 LPSTRT VDD RSVD RSVD XTAL_O XTAL_I VSS VDD VSS RX RX VSS VDD VDD VSS RES VSS RSVD VSS VDD TX TX VDD VSS RSVD RSVD CS8952 100 pin TQFP 14 mm x 14 mm 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 1...

Page 69: ...m clock rate is 16 67 MHz This clock may be asynchronous to RX_CLK and TX_CLK MDIO Management Data Input Output Bi Directional Pin 27 Bi directional signal used to transfer management data between the CS8952 and the Ethernet controller In order to conform with Annex 22B of the IEEE 802 3u specification the MII_DRV pin should be pulled high during power up or reset and the MDIO pin should have an e...

Page 70: ...al drive strength will be added to the MII output drivers This pin includes a weak internal pull down 20 KΩ or the value may be set by an external 4 7 KΩ pull up or pull down resistor In order to conform with Annex 22B of the IEEE 802 3u specification this pin should be pulled high during power up or reset and should have an external 33 Ω series resistor For systems not required to drive external ...

Page 71: ...utput Pin 32 Receive data output Receive data is present when RX_DV is asserted RXD0 is the least significant bit For MII modes nibble wide data synchronous to RX_CLK is transferred on pins RXD 3 0 In 10 Mb s serial mode pin RXD0 is used as the serial output pin and RXD 3 1 are ignored When either BP4B5B or BPALIGN is selected pin RXD4 contains the most significant bit of the five bit code group A...

Page 72: ...e pin TXD0 is used as the serial input pin and TXD 3 1 are ignored When either BP4B5B or BPALIGN is selected pin TXD4 contains the most significant bit of the five bit code group Control and Status Pins 10BT_SER 10 Mb s Serial Mode Select Input Pin 23 When asserted high during power up or reset and 10 Mb s operation is selected serial data will be transferred on pins RXD0 and TXD0 When low during ...

Page 73: ...ent Register address 04h These pins are pulled to M through weak internal resistors 150 KΩ Other values may be set by tying them directly to VDD_MII or VSS or through external 10 KΩ pull up or pull down resistors 1 M 10 Mb s Forced Full M 0 100 Mb s Forced Half M 1 100 Mb s Forced Full M M 100 10 Mb s Auto Neg Full Half 0 0 10 Mb s Auto Neg Half 0 1 10 Mb s Auto Neg Full 1 0 100 Mb s Auto Neg Half...

Page 74: ... TXD 4 0 The receiver will output five bit data with no attempt to identify code group boundaries therefore the data in one RXD 4 0 word may contain data from two code groups Symbol alignment may also be bypassed under software control through bit 12 of the Loopback Bypass and Receiver Error Mask Register address 18h At power up or at reset the value on this pin is latched into bit 12 of the Loopb...

Page 75: ...compatible CMOS input pin LED3 Link Good LED Open Drain Output Pin 71 This active low output indicates the CS8952 has detected a valid link This pin can be simultaneously connected to an LED and to a TTL compatible CMOS input pin LED4 Polarity Full Duplex LED Open Drain Output Pin 72 This active low output indicates 1 for 100 Mb s operation the CS8952 is in full duplex operation 2 for 10 Mb s oper...

Page 76: ... the MDC pin toggles This pin includes a weak internal pull down 20 KΩ or the value may be set by an external 4 7 KΩ pull up or pull down resistor PWRDN Power Down Input Pin 64 When this pin is asserted high the CS8952 powers down all circuitry except that circuitry needed to maintain the network line impedance This is the lowest power mode possible The CS8952 will remain in low power mode until t...

Page 77: ... high when the CS8952 is configured for 100 Mb s operation This pin can be used to drive a low current LED to indicate 100 Mb s operation TCM Transmit Clock Mode Initialization Input Pin 59 The logic value on this three level pin during power up or reset determines whether TX_CLK is used as an input or an output and whether an external 25 MHz clock reference is provided on the CLK25 output pin TES...

Page 78: ... receives signal detection indication from an external optical module TX_NRZ TX_NRZ FX Transmit Differential Output Pair Pins 5 and 4 PECL output pair drives 100 Mb s NRZI encoded data to an external optical module General Pins CLK25 25 MHz Clock Output Pin 17 A 25 MHz Clock is output on this pin when the CS8952 is configured to use an external reference transmit clock in TX_CLK IN MASTER mode See...

Page 79: ...e connected to XTAL_I and XTAL_O left open NOTE The XTAL_I pin capacitive load may be as high as 35pF Any external clock source connected to this pin must be capable of driving larger capacitive loads RSVD Reserved Pins 74 75 76 77 84 98 and 99 These seven pins are reserved and should be tied to VSS VDD_MII MII Power Pins 21 34 and 66 These pins provide power to the CS8952 MII interface Typically ...

Page 80: ...06 0 05 0 15 B 0 007 0 011 0 17 0 27 D 0 618 0 642 15 70 16 30 D1 0 547 0 555 13 90 14 10 E 0 618 0 642 15 70 16 30 E1 0 547 0 555 13 90 14 10 e 0 016 0 024 0 40 0 60 L 0 018 0 030 0 45 0 75 0 000 7 000 0 00 7 00 Nominal pin pitch is 0 50 mm Controlling dimension is mm JEDEC Designation MS026 100L TQFP PACKAGE DRAWING E1 E D1 D 1 e L B A1 A ...

Page 81: ... Notes ...

Page 82: ......

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