Cirrus Logic CS5374 Manual Download

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CS5374

9.3 AMP2CFG: 0x02

(MSB)7

(LSB)0

PWDN2

HP2

MUX2_1

MUX2_0

---

GAIN2_2

GAIN2_1

GAIN2_0

R/W

Figure 22. Amplifier 2 Configuration Register AMP2CFG

Bit definitions:

PWDN2

Amplifier 2 Power Down
1: enable
0: disable

HP2

Amplifier 2 High Precision
1: enable
0: disable

5:4

MUX2[1:0] Input Multiplexer

11: INA2 + INB2
10: INA2 only
01: INB2 only
00: 800 ohm termination

---

Reserved

2:0

GAIN2[2:0] Amplifier 2 Gain

111: reserved
110: 64x
101: 32x
100: 16x
011: 8x
010: 4x
001: 2x
000: 1x

Address: 0x02

Not defined
(read as 0)

Readable

Writable

R/W

Readable

and Writable

Bits in bottom rows
are reset condition

Reset Condition : 0000_0000 (0x00) : Default value

Normal Operation : 00MM_0GGG : MUX and GAIN select

Power Down Operation : 1000_0000 (0x80) : PWDN enabled

Summary of Contents for CS5374

Page 1: ...mmable gain differential amplifi er that buffers analog signals into a high performance fourth order ΔΣ modulator The low noise ΔΣ modulator converts the analog signal into a one bit serial bit stream suitable for the CS5376A digital filter Each amplifier has two sets of external inputs INA and INB to simplify system design as inputs from a hydro phone sensor or the CS4373A test DAC An internal 80...

Page 2: ...ST 19 4 3 Modulator Output MDATA 19 4 3 1 Modulator One s Density 19 4 3 2 Decimated 24 bit Output 19 4 4 Modulator Stability MFLAG 20 4 5 Modulator Clock Input MCLK 20 4 6 Modulator Synchronization MSYNC 20 5 SPITM SERIAL PORT 21 5 1 SPI Pin Descriptions 21 5 2 SPI Serial Transactions 21 5 3 SPI Registers 23 5 3 1 VERSION 0x00 23 5 3 2 AMP1CFG 0x01 23 5 3 3 AMP2CFG 0x02 23 5 3 4 ADCCFG 0x03 24 5 ...

Page 3: ...4 to CS5376A Digital Interface 15 Figure 13 CS5374 Amplifier Block Diagram 16 Figure 14 CS5374 Modulator Block Diagram 18 Figure 15 SPI Interface Block Diagram 21 Figure 16 CS5374 Slave Serial Transactions with CS5376A Master 22 Figure 17 Power Mode Diagram 29 Figure 18 Voltage Reference Circuit 30 Figure 19 Power Supply Diagram 32 Figure 20 Hardware Version ID Register VERSION 35 Figure 21 Amplif...

Page 4: ...esult in permanent damage to the device Normal operation is not guaranteed at these extremes Notes 5 Transient currents up to 100mA will not cause SCR latch up 6 Includes continuous over voltage conditions on the analog input pins Parameter Symbol Min Nom Max Unit Bipolar Power Supplies Positive Analog 2 VA 2 45 2 50 2 55 V Negative Analog Note 1 2 VA 2 45 2 50 2 55 V Positive Digital 3 VD 3 20 3 ...

Page 5: ...ain GAIN x1 x64 Common Mode Gain Note 7 GAINCM x1 Common Mode Voltage Vcm VA 2 5 V Voltage Range Signal Vcm x1 x2 x64 VIN VA 0 7 VA 0 7 VA 1 25 VA 1 75 V Full Scale Differential Input x1 x2 x4 x8 x16 x32 x64 VINFS 5 2 5 1 25 625 312 5 156 25 78 125 Vpp Vpp Vpp mVpp mVpp mVpp mVpp Differential Input Impedance ZINDIFF 1 20 TΩ pF Common Mode Input Impedance ZINCM 0 5 40 TΩ pF Input Bias Current IIN 1...

Page 6: ...or Inputs Input Signal Frequencies Note 9 VBW DC 2000 Hz Full scale Differential AC Input VAC 5 Vpp Full scale Differential DC Input VDC 2 5 2 5 VDC Input Common Mode Voltage VCM VA 2 5 V Input Voltage Range Vcm Signal VRNG VA 0 7 VA 1 25 V Differential Input Impedance INR INF ZDIFINR ZDIFINF 20 1 kΩ MΩ Single ended Input Impedance INR INF ZSEINR ZSEINF 40 2 kΩ MΩ External Anti alias Filter Series...

Page 7: ...Range 1 4 ms DC to 1720 Hz 1x Gain Multiple OWRs 1 2 ms DC to 860 Hz Note 9 12 1 ms DC to 430 Hz 2 ms DC to 215 Hz 4 ms DC to 108 Hz 8 ms DC to 54 Hz 16 ms DC to 27 Hz SNR 121 105 120 123 126 129 131 135 dB dB dB dB dB dB dB Dynamic Range 1x Multiple Gains 1 ms OWR 2x Note 9 12 3x 8x 16x 32x 64x SNR 121 123 122 120 116 111 105 98 dB dB dB dB dB dB dB Channel Distortion Total Harmonic Distortion 1x...

Page 8: ...r 20 Offset calibration is performed in the CS5376A digital filter and includes the full scale signal range Parameter Symbol CS5374 Unit Min Typ Max Channel Gain Accuracy Channel Gain Offset Corrected Note 3 14 GAINLSB 6101194 0xA2E736 6101194 0x5D18CA LSB LSB Absolute Gain Accuracy Note 3 15 GAINABS 1 2 Relative Gain Accuracy 2x Note 16 4x 8x 16x 32x 64x GAINREL 0 3 0 1 0 1 0 1 0 4 0 4 0 3 0 1 Ga...

Page 9: ...CS5374 CS5374 9 CHANNEL PERFORMANCE PLOTS Figure 3 CS5374 Noise Performance 1x Gain Figure 4 CS5374 CS4373A Test DAC Dynamic Performance ...

Page 10: ... Times Except MCLK tRISE 100 ns Input Fall Times Except MCLK tFALL 100 ns Digital Outputs High level Output Voltage Iout 40 μA VOH VD 0 3 V Low level Output Voltage Iout 40 μA VOL 0 3 V High Z Leakage Current IOZ 1 10 μA Digital Output Capacitance COUT 9 pF Output Rise Times Note 22 tRISE 100 ns Output Fall Times Note 22 tFALL 100 ns 0 9 VD 0 1 VD t fall t rise Figure 5 Digital Rise and Fall Times...

Page 11: ...er Symbol Min Typ Max Unit Master Clock Input MCLK Frequency Note 23 fMCLK 2 048 MHz MCLK Duty Cycle MCLKDTC 40 60 MCLK Rise Time tRISE 50 ns MCLK Fall Time tFALL 50 ns MCLK Jitter in band or aliased in band MCLKIBJ 300 ps MCLK Jitter out of band MCLKOBJ 1 ns Master Sync Input MSYNC Setup Time to MCLK Falling Note 24 tMSS 20 366 ns MSYNC Period Note 24 tMSYNC 40 976 ns MSYNC Hold Time after MCLK F...

Page 12: ...ing t3 60 ns SCK High Time t4 120 ns SCK Low Time t5 120 ns SCK Falling Prior to CS Disable t6 60 ns SDO Read Timing SCK Falling to New Data Bit t7 90 ns SCK High Time t8 120 ns SCK Low Time t9 120 ns SCK Falling Hold Time Prior to CS Disable t10 60 ns MSB MSB 1 LSB t6 t5 t4 t3 t2 t1 CS SDI SCK Figure 8 SDI Write Timing in SPI Slave Mode MSB MSB 1 LSB t9 t8 t7 CS SDO SCK t10 Figure 9 SDO Read Timi...

Page 13: ...e 26 ID 50 100 μA Power Supply Current ch1 or ch2 only Analog Power Supply Current Note 26 IA 6 5 8 mA Digital Power Supply Current Note 26 ID 25 50 μA Power Down Current MCLK enabled Analog Power Supply Current Note 26 IA 150 250 μA Digital Power Supply Current Note 26 ID 10 75 μA Power Down Current MCLK disabled Analog Power Supply Current Note 26 IA 2 15 μA Digital Power Supply Current Note 26 ...

Page 14: ... ranges Both the input multiplex er and gain are set by registers accessed through a standard SPI port Each fourth order ΔΣ modulator has very high dy namic range combined with low total harmonic dis tortion and low power consumption It converts differential analog signals from the amplifier to an oversampled ΔΣ serial bit stream which is decimat ed by the CS5376A digital filter to a 24 bit output...

Page 15: ...ydrophone Sensor VA 0 1 VA 0 1 μF μF Test DAC CS4373A 0 02 C0G 0 02 C0G 680 680 680 680 μF μ Ω Ω Ω Ω F 0 02 C0G 0 02 C0G 680 680 680 680 μF μ Ω Ω Ω F Ω VA 0 1 VA 0 1μF μF 0 01μF 2 5V Precision Voltage Reference To CS5376A Digital Control Figure 12 CS5374 to CS5376A Digital Interface Reset Clock and Synchronization MFLAG1 MDATA1 MCLK MSYNC MFLAG2 MDATA2 4 th Order ΔΣ Modulator 4 th Order ΔΣ Modulat...

Page 16: ...and INB switches simultaneously significant current should not be driven through them in this mode The CS5374 mux switches will maintain good linearity only with minimal signal current 3 1 2 Gain Settings GAIN The CS5374 supports gain ranges of 1x 2x 4 x 8x 16x 32x and 64x Amplifier gain is selected using internal configuration registers accessed through the SPI port see the SPITM Register Summary...

Page 17: ... 25 V 1 1 V SIG 0 15 V 1 25 V 1 4 V SIG is 2 5 V relative to SIG For the reverse case SIG 0 15 V 1 25 V 1 4 V SIG 0 15 V 1 25 V 1 1 V SIG is 2 5 V relative to SIG The total swing for SIG relative to SIG is 2 5 V 2 5 V 5 Vpp A similar calculation can be done for SIG relative to SIG Note that a 5 Vpp differential signal centered on a 0 15 V common mode voltage never exceeds 1 1 V and never drops bel...

Page 18: ...width limited to ensure modulator loop stability and pre vent high frequency signals from aliasing into the measurement bandwidth The use of simple sin gle pole differential low pass RC filters across the INR and INF inputs ensures high frequency signals are rejected before they can alias into the measurement bandwidth The approximate 3 dB corner of the input anti alias filter is nominally set to ...

Page 19: ...60 mV channel 1 and 35 mV channel 2 of internal differential offset during conversion to push idle tones out of the measure ment bandwidth Care should be taken to ensure external offset voltages do not negate the internally added differential offset or idle tones will reap pear 4 3 Modulator Output MDATA The CS5374 modulators are designed to operate with the CS5376A digital filter The digital filt...

Page 20: ...rantee full ana log performance requiring a crystal or VCXO based system clock input to the digital filter Clock jitter on the digital filter CLK input directly trans lates to jitter on MCLK 4 6 Modulator Synchronization MSYNC The CS5374 modulators are designed to operate synchronously with other modulators in a distribut ed measurement network so a rising edge on the MSYNC input resets the intern...

Page 21: ...cks to SCLK while writing serial data into SDI or reading serial data out from SDO The CS5374 serial port operates in SPI mode 0 0 0 and reads or writes configuration registers us ing standard 8 bit SPI opcodes Each individual se rial transaction is 24 bits long and is generated by concatenating an 8 bit SPI command opcode an 8 bit register address and an 8 bit data byte as shown in Figure 16 on p...

Page 22: ...from CS5376A SPI2 CS CS 0x03 ADDR DATA Instruction Opcode Address Definition Write 0x02 ADDR 7 0 Write SPI register specified by the address in ADDR Read 0x03 ADDR 7 0 Read SPI register specified by the address in ADDR MSB LSB X 6 1 2 3 4 5 MSB LSB 6 1 2 3 4 5 1 8 2 7 6 5 4 3 SPI Mode 0 Transaction Details SPI2CMD 15 8 SPI2CMD 7 0 SPI2DAT 23 16 SPI2CMD 15 8 SPI2CMD 7 0 SPI2DAT 23 16 ...

Page 23: ...ndition 0000_0000 Normal Operation 00MM_0GGG Power Down Operation 1000_0000 5 3 3 AMP2CFG 0x02 The AMP2CFG register controls the amplifier MUX and GAIN settings for channel 2 It also en ables PWDN mode for the channel 2 amplifier Reset Condition 0000_0000 Normal Operation 00MM_0GGG Power Down Operation 1000_0000 Name Addr Type Bits Description VERSION 0x00 R 8 Device Version ID AMP1CFG 0x01 R W 8 ...

Page 24: ...for nor mal operation SPI Write Transactions Transaction CS5374 SPI Write Description 01 SI 02 01 20 SO Write AMP1CFG register 0x01 CH1 INA enabled 1x gain 0x20 02 SI 02 02 20 SO Write AMP2CFG register 0x02 CH2 INA enabled 1x gain 0x20 03 SI 02 03 40 SO Write ADCCFG register 0x03 Normal operation 0x40 04 SI 02 04 8F SO Write PWRCFG register 0x04 Normal operation 0x8F SPI Read Transactions Transact...

Page 25: ...lter registers using the primary SPI 1 port is described in the CS5376A data sheet GPIO Register Certain GPIO pins on the CS5376A have dual use as chip selects for the SPI 2 port The GPIO0 CS0 and GPIO1 CS1 pins are recommended as dedicat ed chip selects when connecting two CS5374 de vices to the CS5376A SPI 2 port To operate the CS0 and CS1 pins as SPI 2 chip selects they must be programmed as ou...

Page 26: ...ns to Write the CS5374 AMP1CFG Register Transaction CS5376A Primary SPI 1 Write Description 01 MOSI 02 03 00 00 01 00 00 11 00 02 01 MISO SPI Command 0x02 Write SPI Address 0x03 SPICMD SPICMD 0x000001 Write Register SPIDAT1 0x000011 SPI2CMD SPIDAT2 0x000201 Write AMP1CFG 02 Delay 1ms monitor SINT or poll E2DREQ See the CS5376A data sheet 03 MOSI 02 03 00 00 01 00 00 12 20 00 00 MISO SPI Command 0x...

Page 27: ...ite Register SPIDAT1 0x000010 SPI2CTRL SPIDAT2 0x3F4162 CS1 Transaction Table 7 Example CS5376A SPI 1 Transactions to Write AMP2CFG and ADCCFG Transaction CS5376A Primary SPI 1 Write Description 01 MOSI 02 03 00 00 01 00 00 11 00 02 03 MISO SPI Command 0x02 Write SPI Address 0x03 SPICMD SPICMD 0x000001 Write Register SPIDAT1 0x000011 SPI2CMD SPIDAT2 0x000203 Write ADCCFG 02 Delay 1ms monitor SINT ...

Page 28: ...O SPI Command 0x02 Write SPI Address 0x03 SPICMD SPICMD 0x000001 Write Register SPIDAT1 0x000012 SPI2DAT SPIDAT2 0x8F0000 Normal Operation 04 Delay 1ms monitor SINT or poll E2DREQ See the CS5376A data sheet 05 MOSI 02 03 00 00 01 00 00 10 3F 01 61 MISO SPI Command 0x02 Write SPI Address 0x03 SPICMD SPICMD 0x000001 Write Register SPIDAT1 0x000010 SPI2CTRL SPIDAT2 0x3F0161 CS0 Transaction 06 Delay 1...

Page 29: ...mpedance In this mode power consumption is reduced but not reduced as low as with MCLK inactive as sections of the dig ital state machine are kept awake to support SPI communications Any unused amplifier modulator channels can be turned off individually through the configuration registers 6 3 Power Down MCLK Disabled If MCLK is stopped an internal loss of clock de tection circuit automatically pla...

Page 30: ...ter is required for each device connected to the voltage reference output Signal dependent sampling of the voltage reference by one system device could cause unwanted tones to ap pear in the measurement bandwidth of another sys tem device if a single VREF RC filter is common to both 7 3 VREF PCB Routing To minimize the possibility of outside noise cou pling into the CS5374 voltage reference input ...

Page 31: ...ccuracy The nominal voltage reference input is specified as 2 500 V across the VREF pins and all CS5374 gain accuracy specifications are measured using a nominal voltage reference input Any variation from a nominal VREF input will proportionally vary the analog full scale gain accuracy Since temperature drift of the voltage reference re sults in gain drift of the analog full scale amplitude care s...

Page 32: ...t ed to mismatched supply rail initialization Care should be taken to connect the CS5374 ther mal pad on the bottom of the package to VA not system ground GND since it internally connects to VA and is expected to be the most negative ap plied voltage 8 2 Digital Power Supply The digital power supply across the VD and GND pins is specified for a 3 3 V power supply The digital power supply should be...

Page 33: ...pecified in the Power Supply Characteristics on page 13 8 6 SCR Latch up Considerations It is recommended to connect the VA power sup ply to system ground GND through a reverse bi ased Schottky diode At power up if the VA power supply ramps up before the VA supply is established the VA pin voltage could be pulled above ground potential through the CS5374 de vice If the VA supply is pulled 0 7 V or...

Page 34: ...tain the hardware configuration settings Name Addr Type Bits Description VERSION 0x00 R 8 Device Version ID AMP1CFG 0x01 R W 8 Amplifier 1 configuration AMP2CFG 0x02 R W 8 Amplifier 2 configuration ADCCFG 0x03 R W 8 Modulator 1 2 configuration PWRCFG 0x04 R W 8 Power configuration ...

Page 35: ...n ID Register VERSION Bit definitions 7 0 VERS Hardware revision ID register 0x41 Revision A Address 0x00 Not defined read as 0 R Readable W Writable R W Readable and Writable Bits in bottom rows are reset condition Reset Condition 0100_0001 0x41 Default value Normal Operation 0100_0001 0x41 Default value Power Down Operation 0100_0001 0x41 Default value ...

Page 36: ...enable 0 disable 5 4 MUX1 1 0 Input Multiplexer 11 INA1 INB1 10 INA1 only 01 INB1 only 00 800 ohm termination 3 GUARD GUARD Output 1 disable 0 enable 2 0 GAIN1 2 0 Amplifier 1 Gain 111 reserved 110 64x 101 32x 100 16x 011 8x 010 4x 001 2x 000 1x Address 0x01 Not defined read as 0 R Readable W Writable R W Readable and Writable Bits in bottom rows are reset condition Reset Condition 0000_0000 0x00 ...

Page 37: ...gh Precision 1 enable 0 disable 5 4 MUX2 1 0 Input Multiplexer 11 INA2 INB2 10 INA2 only 01 INB2 only 00 800 ohm termination 3 Reserved 2 0 GAIN2 2 0 Amplifier 2 Gain 111 reserved 110 64x 101 32x 100 16x 011 8x 010 4x 001 2x 000 1x Address 0x02 Not defined read as 0 R Readable W Writable R W Readable and Writable Bits in bottom rows are reset condition Reset Condition 0000_0000 0x00 Default value ...

Page 38: ...35mV to Channel 2 1 disable 0 enable 6 HP Modulator High Precision 1 enable 0 disable 5 PWDN2 Modulator 2 Power Down 1 enable 0 disable 4 PWDN1 Modulator 1 Power Down 1 enable 0 disable 3 0 Reserved Address 0x03 Not defined read as 0 R Readable W Writable R W Readable and Writable Bits in bottom rows are reset condition Reset Condition 0000_0000 0x00 Default value Normal Operation 0100_0000 0x40 H...

Page 39: ...11 2 3 10 1 3 01 4 3 00 nominal current 3 rough Modulator Rough Phase 1 reduced current 0 nominal current 2 i1_tail Amplifier i1 Tail Current 1 reduced current 0 nominal current 1 0 amp_i5 Amplifier i5 Bias 11 7 11 10 9 13 01 15 13 00 nominal current Address 0x04 Not defined read as 0 R Readable W Writable R W Readable and Writable Bits in bottom rows are reset condition Reset Condition 0000_0000 ...

Page 40: ...l Communications Interface INB2 INB2 9 10 I Channel 2 differential analog input B Selected via Serial Communications Interface INA2 INA2 11 12 I Channel 2 differential analog input A Selected via Serial Communications Interface INA2 INA2 11 12 Top Down Though Package View Pin 1 Location Indicators INA1 INA1 INB1 INB1 DNC VA VA DNC INB2 INB2 1 2 3 4 5 6 7 MCLK MSYNC MDATA1 MFLAG1 36 35 34 33 VD GND...

Page 41: ...nd fine inputs From the Channel 2 differential anti alias filter Voltage Reference VREF VREF 21 22 I Voltage reference input Refer to the Specified Operating Conditions Serial Interface CS 25 I Chip select Active low SCLK 26 I Serial clock SDI 27 I Serial data in to device SDO 28 O Serial data out of device Modulator Interface MCLK 36 I Modulator clock input MSYNC 35 I Modulator sync input MFLAG1 ...

Page 42: ...CS5374 CS5374 42 11 PACKAGE DIMENSIONS 48 PIN QFN 7MM X 7MM ...

Page 43: ...URING HANDLING INFORMATION MSL Moisture Sensitivity Level as specified by IPC JEDEC J STD 020 Model Number Temperature Package CS5374 CNZ lead Pb free 10 to 70 C 48 Pin QFN Model Number Peak Reflow Temp MSL Rating Max Floor Life CS5374 CNZ lead Pb free 260 C 3 7 Days ...

Page 44: ... of Cirrus and by furnishing this information Cirrus grants no license express or implied under any patents mask work rights copyrights trademarks trade secrets or other intellectual property rights Cirrus owns the copyrights associated with the information contained herein and gives con sent for copies to be made of the information only for use within your organization with respect to Cirrus inte...

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