
37
APPENDIX G: UDSP SCHEMATICS
GND
+15V
-15V
SPDIF I/O
POWER/CONTROL2
ANALOG I/O
CONTROL1
SERIAL AUDIO I/O 1
+5V
FOR PHIHONG PSA-46-304
SERIAL AUDIO I/O 2
MICROCONTROLLER
MICRO
5V_MRESETn
2V_DSP1_RESETn
CSn2
CSn0
CSn4
5V_MOSI
5V_SCK
ADDR15
ADDR16
ADDR17
5V_MISO
2V_MOSI
2V_MISO
2V_SCK
BMCTRL1
CSn3
CSn1
ADDR18
2V_DSP2_RESETn
MUTECTRL1
2V_DBDA
2V_DBCK1
2V_DBCK2
RXD
TXD
CSn7
CSn5
CSn6
MUTECTRL0
BMCTRL0
MUTECTRL2
RTS
CTS
EMAD[7..0]
DSP_RDn
DSP_WRn
EXTMEMn
IRQn[5..0]
DAP_MCLK
DAP_SCLK
DAP_LRCLK
DSP1_CDI_SCLK
DSP1_DAI_SCLK
DSP2_DAI_SCLK
DSP2_CDI_SCLK
DSP1_CDI_LRCLK
DSP2_CDI_LRCLK
DSP2_CDI_SDIN
DSP1_CDI_SDIN
DSP1_DAI_SDIN
DSP2_DAI_SDIN
DSP2_DAI_LRCLK
DSP1_DAI_LRCLK
DAP_SDOUT[8..1]
DSP1_DAO_MCLK
DSP1_DAO_SCLK
DSP1_DAO_LRCLK
DSP2_DAO_LRCLK
DSP2_DAO_SCLK
DSP2_DAO_MCLK
2V_MRESETn
PP_CTRL[2..0]
PP_STROBEn
PP_ACKn
PP_D[7..0]
PP_STATUS[3..0]
DAP_SDIN[4..1]
DSP1_DAO_SDOUT[4..1]
DSP2_DAO_SDOUT[4..1]
ADC_MCLK
ADC_SCLK
ADC_LRCLK
ADC_SDOUT[4..1]
SPDIF_RX2
SPDIF_LRCLK
SPDIF_SCLK
SPARE[6..0]
SPDIF_TX1
SPDIF_SDOUT
SPDIF_RX1
SPDIF_TX2
SPDIF_MCLK
SPDIF_TX3
SPDIF_RX3
ADC_DIF[1..0]
SPDIF_TX4
RS422_DATA1
RS422_CLK1
RS422_CLK2
DIP_MODE_SEL[7..0]
HACK
DC_OSC
Digital Audio Port (DAP)
DAP
DAP_LRCLK
DAP_SCLK
DAP_MCLK
DAP_SDOUT[8..1]
DAP_SDIN[4..1]
SPDIF I/O
SPDIF
SPDIF_RX2
SPDIF_RX3
SPDIF_RX4
SPDIF_RX1
SPDIF_TX2
SPDIF_TX1
SPDIF_TX3
SPDIF_RXN0
SPDIF_RXP0
SPDIF_TX4
PARALLEL PORT
PPORT
PP_D[7..0]
PP_STROBEn
PP_ACKn
PP_STATUS[3..0]
PP_CTRL[2..0]
HEADPHONE
HEADPHONE
AIO[10..1]]
RS422 BUFFER
RS422
RS422_DATA1
RS422_CLK1
RS422_CLK2
Power
Power
+15VBUS
GND
-15VBUS
+5VD
RS232 Interface
RS232
RXD
TXD
RTS
CTS
+15VBUS
-15VBUS
AIO12
AIO11
SPDIF_RX1
SPDIF_RX2
SPDIF_RX4
SPDIF_RX3
GND
SPDIF_TX1
AIO13
AIO14
AIO15
AIO16
GND
2V_DBCK1
SPDIF_TX1
+15VBUS
GND
2V_DSP2_RESETn
GND
+5VD
SPDIF_RXP0
2V_DBDA
-15VBUS
GND
GND
+5VD
5V_MRESETn
GND
EXTMEMn
SPDIF_RX4
SPDIF_RX2
+15VBUS
GND
SPDIF_RX1
-15VBUS
GND
SPDIF_RXN0
GND
GND
+2.5V
GND
GND
+3.3V
EMOEn
+3.3V
2V_MRESETn
SPDIF_TX3
GND
2V_DSP1_RESETn
+2.5V
GND
GND
SPDIF_RX3
2V_DBCK2
GND
SPDIF_TX2
DSP1_CDI_SCLK
DSP1_CDI_LRCLK
DSP1_CDI_SDIN
DSP1_DAI_SCLK
DSP1_DAI_LRCLK
DSP1_DAI_SDIN
DSP1_DAO_MCLK
DSP1_DAO_SCLK
DSP1_DAO_LRCLK
DSP2_DAO_SCLK
DSP2_DAI_LRCLK
DSP2_DAO_MCLK
DSP2_DAO_LRCLK
DSP2_CDI_LRCLK
DSP2_CDI_SCLK
DSP2_DAI_SCLK
DSP2_DAI_SDIN
DSP2_CDI_SDIN
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
MUTECTRL2
MUTECTRL0
BMCTRL0
ADDR15
ADDR17
SPARE4
2V_SCK
2V_MOSI
5V_SCK
5V_MOSI
BMCTRL1
GND
GND
GND
2V_MISO
ADDR18
MUTECTRL1
GND
DSP_WRn
5V_MISO
GND
ADDR16
+5VD
SPDIF_TX3
SPDIF_RXP0
SPDIF_RXN0
-15VBUS
+5VD
+15VBUS
GND
ADC_LRCLK
ADC_SDOUT3
ADC_SDOUT1
ADC_MCLK
SPDIF_SDOUT
SPDIF_SCLK
SPDIF_MCLK
ADC_SDOUT2
GND
ADC_SCLK
SPDIF_LRCLK
GND
GND
ADC_SDOUT4
GND
GND
GND
SPDIF_TX4
SPDIF_TX2
SPDIF_TX4
AIO16
AIO15
AIO13
AIO14
AIO10
AIO9
AIO11
AIO12
AIO6
AIO5
AIO7
AIO8
AIO2
AIO1
AIO3
AIO4
AIO10
AIO9
AIO8
AIO7
AIO5
AIO6
AIO4
AIO2
AIO3
AIO1
RS422_DATA1
RS422_CLK1
RS422_CLK2
DIP_MODE_SEL6
DIP_MODE_SEL7
DIP_MODE_SEL3
DIP_MODE_SEL5
DIP_MODE_SEL0
DIP_MODE_SEL2
DIP_MODE_SEL1
DIP_MODE_SEL4
DC_OSC
IRQn[5..0]
DSP1_DAO_SDOUT4
IRQn4
SPDIF_SCLK
ADC_SDOUT[4..1]
DSP1_DAO_LRCLK
DSP2_CDI_SCLK
BMCTRL0
MUTECTRL0
CSn5
5V_MOSI
EMAD[7..0]
SPARE2
PP_STROBEn
DSP2_DAO_MCLK
DSP2_CDI_LRCLK
DAP_SCLK
CSn6
TXD
SPDIF_RX3
PP_D[7..0]
BMCTRL1
2V_DSP1_RESETn
IRQn2
EMAD0
SPARE5
EMAD3
2V_DBDA
RS422_DATA1
SPDIF_MCLK
ADC_LRCLK
DSP2_DAI_SCLK
EMOEn
CTS
CSn0
EMAD1
DSP1_DAO_SDOUT2
DSP1_DAO_SDOUT3
2V_DBCK1
DSP1_DAO_MCLK
RXD
2V_SCK
EMAD5
IRQn3
DSP2_DAO_SDOUT[4..1]
DSP2_DAI_LRCLK
2V_DBCK2
CSn3
CSn2
DSP1_DAO_SDOUT[4..1]
ADC_DIF[1..0]
DSP1_DAO_SDOUT1
EMAD6
SPDIF_TX4
SPDIF_RX2
ADC_SCLK
DSP1_DAI_SDIN
IRQn[5..0]
DSP_WRn
2V_DBDA
SPARE[6..0]
SPARE3
DSP2_DAO_SDOUT3
DSP2_DAO_LRCLK
SPDIF_TX3
SPDIF_RX1
ADC_MCLK
PP_STATUS[3..0]
2V_MISO
DSP2_DAO_SDOUT1
IRQn5
ADC_DIF[1..0]
DSP1_DAO_SDOUT[4..1]
DSP1_CDI_SDIN
DSP1_CDI_LRCLK
IRQn[5..0]
SPARE[6..0]
EMAD[7..0]
DSP2_DAO_SDOUT[4..1]
SPARE0
2V_DBCK2
DIP_MODE_SEL[7..0]
DSP1_DAO_SCLK
DAP_LRCLK
RTS
SPARE[6..0]
SPARE6
DSP2_DAO_SDOUT2
SPDIF_TX2
SPDIF_SDOUT
SPARE[6..0]
DSP1_DAI_SCLK
DSP1_CDI_SCLK
IRQn1
SPARE4
RS422_CLK2
PP_ACKn
DAP_SDOUT[8..1]
DSP2_CDI_SDIN
DAP_MCLK
5V_MISO
5V_MRESETn
DSP2_DAO_SDOUT[4..1]
EMAD4
ADC_DIF1
IRQn0
ADC_DIF0
PP_CTRL[2..0]
2V_MRESETn
DSP2_DAO_SCLK
DSP1_DAI_LRCLK
2V_DSP2_RESETn
SPARE1
SPDIF_LRCLK
DAP_SDIN[4..1]
ADDR18
DSP1_DAO_SDOUT[4..1]
EMAD2
DSP2_DAO_SDOUT4
EMAD7
2V_DBCK1
2V_MOSI
SPARE[6..0]
RS422_CLK1
SPDIF_TX1
DSP2_DAI_SDIN
EMAD[7..0]
MUTECTRL2
MUTECTRL1
5V_SCK
EXTMEMn
HACK
DC_OSC
CSn1
CSn3
CSn7
ADDR16
CSn6
CSn5
CSn4
CSn[7..0]
CSn[7..0]
CSn7
CSn1
CSn0
CSn2
CSn4
ADDR17
ADDR15
AIO[10..1]
AIO[16..1]
+2.5V
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
+5VD
+3.3V
+2.5V
J15
PHONO JACK RA
J18
PHONO JACK RA
1
2
J32
TERMINAL GREEN
1
J17
PHONO JACK RA
J16
PHONO JACK RA
1
2
J21
PHONO JACK RA
1
2
J36
HEADER 3X2
1
2
3
4
5
6
J22
PHONO JACK RA
P1
SOCKET 16X2-2MM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P6
SOCKET 20X2-2MM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
J19
PHONO JACK RA
J30
TERMINAL BLACK
1
J28
TERMINAL BLUE
1
J35
DIN5M
1
2
3
4
5
6
P3
SOCKET 20X2-2MM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
J27
PHONO JACK RA
1
2
R11
4.7k
J25
PHONO JACK RA
1
2
J23
PHONO JACK RA
1
2
J31
PHONO JACK RA
1
2
P5
SOCKET 20X2-2MM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
J34
TERMINAL RED
1
J29
PHONO JACK RA
1
2
J33
PHONO JACK RA
1
2
R12
4.7k
P2
SOCKET 20X2-2MM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P4
SOCKET 7X2-2MM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
J26
PHONO JACK RA
J20
PHONO JACK RA
1
2
R13
4.7k
J24
PHONO JACK RA
HACK
DC_OSC
Figure 22. UDSP - Top
Summary of Contents for CS49300
Page 16: ...16 APPENDIX D SCHEMATICS Figure 6 Control and Data I O ...
Page 17: ...17 Figure 7 DSP ...
Page 18: ...18 Figure 8 External Memory ...
Page 19: ...19 Figure 9 CoDec ...
Page 20: ...20 Figure 10 External A D Converters ...
Page 21: ...21 Figure 11 L R Input Filters ...
Page 22: ...22 Figure 12 Ls Rs Input Filters ...
Page 23: ...23 Figure 13 C Sub Input Filters ...
Page 24: ...24 Figure 14 SBL SBR Input Filters ...
Page 25: ...25 Figure 15 L R Output Filters ...
Page 26: ...26 Figure 16 Ls Rs Output Filters ...
Page 27: ...27 Figure 17 C Sub Output Filters ...
Page 28: ...28 Figure 18 SBL SBR Output Filters ...
Page 29: ...29 APPENDIX E LAYOUT PLOTS GROUND PLANE VIAS ARE FLOODED Figure 19 Top Layer ...
Page 30: ...30 Figure 20 Bottom Layer ...
Page 31: ...31 Figure 21 Assembly Drawing ...
Page 50: ......