Cirrus Logic CS2000-OTP, General Description Manual, Page: 24 / 30

CS2000-OTP
24 DS758F3
6.3 Global Configuration Parameters
6.3.1 AUX PLL Lock Output Configuration (AuxLockCfg)
When the AUX_OUT pin is configured as a lock indicator (
AuxOutSrc[1:0]
modal parameter = ‘11’), this
global parameter configures the AUX_OUT driver to either push-pull or open drain. It also determines the
polarity of the lock signal. If AUX_OUT is configured as a clock output, the state of this parameter is dis-
regarded.
Note:
AUX_OUT is an
un
lock indicator, signalling an error condition when the PLL is unlocked. There-
fore, the pin polarity is defined relative to the
un
lock condition.
6.3.2 Reference Clock Input Divider (RefClkDiv[1:0])
Selects the input divider for the timing reference clock.
6.3.3 Enable PLL Clock Output on Unlock (ClkOutUnl)
Defines the state of the PLL output during the PLL unlock condition.
6.3.4 Low-Frequency Ratio Configuration (LFRatioCfg)
Determines how to interpret the currently indexed 32-bit User Defined Ratio when the dynamic ratio based
Hybrid PLL Mode is selected (either manually or automatically, see
section 5.4.5 on page 15 ).
Note:
When the static ratio based Frequency Synthesizer Mode is selected (either manually or auto-
matically), the currently indexed User Defined Ratio will always be interpreted as a 12.20 fixed point value,
regardless of how this parameter is set.
AuxLockCfg AUX_OUT Driver Configuration
0 Push-Pull, Active High (output ‘high’ for unlocked condition, ‘low’ for locked condition).
1 Open Drain, Active Low (output ‘low’ for unlocked condition, high-Z for locked condition).
Application:
“Auxiliary Output” on page 18
RefClkDiv[1:0] Reference Clock Input Divider REF_CLK Frequency Range
00 ÷ 4. 32 MHz to 56 MHz (50 MHz with XTI)
01 ÷ 2. 16 MHz to 28 MHz
10 ÷ 1. 8 MHz to 14 MHz
11 Reserved.
Application:
“Internal Timing Reference Clock Divider” on page 11
ClkOutUnl Clock Output Enable Status
0 Clock outputs are driven ‘low’ when PLL is unlocked.
1 Clock outputs are always enabled (results in unpredictable output when PLL is unlocked).
Application:
“PLL Clock Output” on page 18
LFRatioCfg Ratio Bit Encoding Interpretation when Input Clock Source is CLK_IN
0 20.12 - High Multiplier.
1 12.20 - High Accuracy.
Application:
“User Defined Ratio (RUD), Frequency Synthesizer Mode” on page 14