Cirrus Logic CDB47xxx, User Manual

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CDB47xxx-DC48 Daughtercard Schematic
CDB47xxx User’s Manual
DS886DB9 Copyright 2012 Cirrus Logic, Inc 6-30
6.4 CDB47xxx-DC48 Daughtercard Schematic
6.4.1 CDB47xxx-DC48 Block Diagram
Figure 6-25 shows the CDB47xxx-DC48 block diagram
6.4.2 CDB47xxx-DC48 Schematic
The schematic for the CDB47xxx-DC48 daughtercard is shown in Figure 6-26 . The CDB47xxx-DC48
employs the CS47048 DSP. The DSP is driven by an external crystal circuit. This fixed 24.576 MHz clock
is used to drive the PLL inside the CS470xx for the core DSP clocks, and for all internal audio clocks.
The DSP has a dedicated reset line (DSP_RESET) that must be driven by the host to initialize the
CS470xx’s communication mode and initiate the first boot sequence. This signal is independent of any
other reset on the board and can be used to sequence device power up.
The host communication protocol of the DSP is determined by the state of the HS[3:0] pins at the rising
edge of reset.
The serial host control port (SCP_CLK, SCP_MOSI, SCP_MISO/SDA, SCP_CS, SCP_IRQ, SCP1_BSY)
is used by the host controller to boot and control the DSP. Note that the pull-up resistors on the SCP_IRQ
and SCP_BSY pins are required for both SPI and I
2
C control, since these are open-drain pins. The pull-
ups on the SCP_CLK and SC1_SDA pins are required only for I
2
C operation.
The DSP has a debug port (DBDA, DBCK) that allows a developer to debug the DSP during normal
operation. This is a slave port that can be connected to an I
2
C master, or it can be simply terminated with
pull-up resistors.
The DAI3 digital audio input pin of the CS470xx is driven by a multiplexer on the CDB47xxx main board
that chooses between optical S/PDIF RX, coaxial S/PDIF RX, and DAI3 from the DAI header on the main
board. The remaining DAI pins are driven directly by the DAI header on the main board.
The DAO port of the CS470xx is driven directly to the DAO header on the main CDB47xxx Board.
The DAC outputs are routed directly to the DAC filter circuitry on the CDB47xxx main board.
The ADC inputs are routed directly to the ADC filter circuitry on the CDB47xxx main board.
The Daughtercard ID register (U2) is used to identify which CS470xx chip is populated on the board. This
register is read by the MCU or the PC in order to determine which DSP firmware is appropriate for the
SOC.