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CDB43131-GBK

CDB43131-GBK Kit Manual

http://www.cirrus.com

Copyright ©

2018 Cirrus Logic, Inc. and

Cirrus Logic International Semiconductor Ltd.

All rights reserved.

DS1155V2DB

1

JUL

'18

Features

•

Configurable serial audio headers for PCM, DSD and DoP audio

•

Headphone and line outputs

•

Analog and S/PDIF audio input

•

USB audio module capability

•

WISCE™ I

2

C-based software control

•

Windows® compatible

Description

The CDB43131-GBK is a dedicated platform for testing and evaluating the CS43131. The CS43131 is a high-performance
audio DAC with integrated impedance detection and headphone drivers. To allow comprehensive testing and evaluation
of the performance of the CS43131, extensive software-configurable options are available through the CDB43131
evaluation kit. The kit also included the CDB-HDR-MEAS, for measuring the 130 dB dynamic range performance of the
CS43131.

Software options, such as register settings for the CS43131, are configured via the WISCE software tool, which
communicates with the CDB43131-GBK via an Aardvark I

2

C/SPI host adapter from a Windows computer, or via Mini-USB

cable.

Figure 1 CDB43131 Board Block Diagram

1
2
3
...
»

Summary of Contents for CDB43131-GBK

Page 1: ...ating the CS43131 The CS43131 is a high performance audio DAC with integrated impedance detection and headphone drivers To allow comprehensive testing and evaluation of the performance of the CS43131 extensive software configurable options are available through the CDB43131 evaluation kit The kit also included the CDB HDR MEAS for measuring the 130 dB dynamic range performance of the CS43131 Softw...

Page 2: ...ck Reference 15 3 1 Register Descriptions 15 4 CDB HDR MEAS High Dynamic Range Measurement Preamplifier 19 4 1 Powering the CDB HDR MEAS 19 4 2 How the CDB HDR MEAS Works 20 5 Testing the CS43131 using WISCE Software 21 5 1 Launching WISCE Software 21 5 2 Loading the CDB43131 board Panel and Register Map 22 5 3 Loading the CS43131 Plugins and Register Map 24 5 4 Initializing the Devices on the CDB...

Page 3: ...hese component boards is described in the following sections 1 1 CDB43131 Board The CDB43131 is shown in the following figure Figure 2 CDB43131 Base Board 1 2 CDB HDR MEAS Board The CDB HDR MEAS is shown in the following figure This board is used for measuring the very low HDR of the device with an Audio Precision SYS 2700 or APx555 audio analyzer Figure 3 CDB HDR MEAS Board ...

Page 4: ...V signals These buffers are controlled by an I O Expander The I O Expander can be controlled through its I2 C interface The register map for I O Expander is described in Section 3 The direction of clock signals is determined by the CS43131 s operating mode master or slave mode The CDB43131 can also communicate with a smart codec through the use of J42 The purpose of using a smart codec is to allow...

Page 5: ...pply rails from external bench supplies via banana jacks The switchers and LDOs step down the 5 V supply to 3 6 V 3 3 V 1 0 V 1 8 V analog and 1 8 V digital levels If the device is set into External VCP_FILT Supply Mode and bypass the internal Class H charge pump circuit then a 3 volt supply must be applied to VCP_FILT and VCP_FILT The banana jacks are connected to each device through a set of res...

Page 6: ...are routed to from the CS43131 using voltage level translation buffers The direction of clock and data through these buffers is controlled using on board TCA6424 I O Expander IC U9 U12 and U15 translate the signals on J25 and J26 from a voltage of 3 3 V or 1 8 V to the operational voltage of 1 8 V The ASP signals are then fed into J24 while the XSP signals are fed into J44 These 3x3 pin headers ar...

Page 7: ...ce jumpers between the two columns of pins labeled BRD and DUT For example in order to send SCLK1 LRCLK1 and SDIN1 signals from the buffer to the DAC place jumpers between pins of the BRD and DUT group as shown in the following figure Figure 6 Jumper Settings to Route Signals from Buffers to DUT ...

Page 8: ... from the APx to LRCLK1 pins in the AP group and the RXDAT1 output from the APx to SDIN1 pins in the AP group as shown in the following figure Figure 7 External Audio Source to DUT 2 2 2 S PDIF Receiver The CS8422 S PDIF receiver provides two channel digital input either from an optical or coax connector The CS8422 can support sample rates up to 211 kHz and data output with either 16 18 20 or 24 b...

Page 9: ... headphone jack for each the CSP J16 and QFN J34 Situated next to each headphone jack are a pair of testpoints J18 J19 and J35 J36 respectively for connecting to an APx Figure 8 1 8 Headphone Jack and APx connectors for CSP Figure 9 1 8 Headphone Jack and APx connectors for QFN ...

Page 10: ... provides an interface to connect a Total Phase Aardvark I2 C SPI Host Adapter The header signals are described in the following table The logic level on these pins is 3 3 V Through this header a user can communicate with a smart codec the TCA6424 I O Expander and the CS43131 Table 4 I2C SPI Header Pinout Header Pins Designation Description J42 1 I2C_SCL I2 C clock 3 I2C_SDA I2 C data 5 SPI_MISO S...

Page 11: ...sence of 5 V rail CDC_3V3 D11 Green Presence of codec 3 3 V rail CDC_1V8 D12 Green Presence of codec 1 8 V rail ERR D3 Red No digital input Off Digital input present VP D17 Green Presence of the CS43131 VP rail VCP D16 Green Presence of the CS43131 VCP rail VA D15 Green Presence of the CS43131 VA rail VL D14 Green Presence of the CS43131 VL rail VD D13 Green Presence of the CS43131 VD rail DAC_INT...

Page 12: ... loading resistance of 16 32 600 Ω for CSP HPOUTA J16 CSP HPIN 3 5mm headphone jack I The headphone in jack for the CS43131 CSP device J17 QFN HPOUTA Loading 3x1x1 header Selectable loading resistance of 16 32 600 Ω for QFN HPOUTA J18 CSP HPINB Test Point 2x1 header O 2 pin test point for Audio Precision J19 CSP HPINA Test Point 2x1 header O 2 pin test point for Audio Precision J20 GND Banana Jack...

Page 13: ...J52 Jumper between 2 3 to get 4 V from USB VBUS J43 J53 I2C DUT Connection 3x2 header Connect shunt between DUT BRD to connect DUT and I2C data Disconnect shunt and use 2 pin test point for Audio Precision between DUT GND to measure I2C data directly J54 RST INT CSP Connection 3x2 header Connect shunt between DUT BRD to connect RST and INT data Disconnect shunt and use 2 pin test point for Audio P...

Page 14: ...S43131 CSP CS43131 QFN 2 8 Codec MCLK Selection The MCLK input to the smart codec can come either from the on board 24 576 MHz clock oscillator a 22 579 MHz clock oscillator MCLK1 from ASP J25 MCLK2 from XSP J26 or from the CLKOUT pin on the DAC or the MCLK output from an external audio source The selection is controlled by WISCE software Figure 12 CODEC MCLK Selection 2 9 Clock Sources The CDB431...

Page 15: ...ED RESER VED Default Value 1 1 1 1 X 1 X X Bits Name Description 7 XTI_OSC_24p576MHZ_EN Enable 24 576 MHz CLK to be used as input to CODEC 0 Enabled 1 Disabled Default 6 XTI_OSC_22p5792MHZ_EN Enable 22 5792 MHz CLK to be used as input to CODEC 0 Enabled 1 Disabled Default 5 XTI_CLKOUT_EN Select SPDIF Clock Master 0 External CLK 1 CS43131 CLKOUT Default 4 XTI_CLKOUT_CSP QFN Select Device to be SPDI...

Page 16: ... DSD 1 SPDIF Default 6 ASP_PCM SPDIF Set Codec in PCM SPDIF Mode 0 PCM 1 SPDIF Default 5 XSP_M S Set XSP as Master Slave 1 Master Default 0 Slave 4 ASP_M S Set ASP as Master Slave 1 Master Default 0 Slave 3 MCLK2_HDR_M S Set Codec as Master to MCLK2 1 Master Default 0 Slave 2 MCLK1_HDR_M S Set Codec as Master to MCLK1 1 Master Default 0 Slave 1 XTI_MCLK2_BRD_EN Enable ASP MCLK to be used as input ...

Page 17: ...OUT _EN_DIR XTI_CLKOUT_CS P QFN_DIR Reser ved RESET_SP DIF_DIR RESET_ DUT2 RESET_ DUT1 Default Value 0 0 0 0 x 0 1 1 Bits Name Description 7 XTI_OSC_24_576MHZ_EN_DIR Direction of the XTI_OSC_24_576MHz_EN signal 0 Output Default 1 Input 6 XTI_OSC_22_5792HZ_EN_DIR Direction of the XTI_OSC_24_5792MHz_EN signal 0 Output Default 1 Input 5 XTI_CLKOUT_EN_DIR Direction of the XTI_CLKOUT_EN signal 0 Output...

Page 18: ...S_DIR Direction of the ASP_M S signal 0 Output Default 1 Input 3 MCLK2_HDR_M S_DIR Direction of the MCLK2_HDR_M S signal 0 Output Default 1 Input 2 MCLK1_HDR_M S_DIR Direction of the MCLK1_HDR_M S signal 0 Output Default 1 Input 1 XTI_MCLK2_BRD_EN_DIR Direction of the XTI_MCLK2_BRD_EN signal 0 Output Default 1 Input 0 XTI_MCLK1_BRD_EN_DIR Direction of the XTI_MCLK1_BRD_EN signal 0 Output Default 1...

Page 19: ...h dynamic range DNR of the CS43131 The CDB HDR MEAS preserves the dynamic range of the input signal while amplifying the input signal by 13 66 dB to overcome noise floor limitations of the audio analyzer 4 1 Powering the CDB HDR MEAS The CDB HDR MEAS board requires a triple output DC power supply capable of providing 15 V and GND connection at 100 mA as shown in the figure below Standard binding p...

Page 20: ...nt the difference results in a measurement error that hampers performance Figure 16 Testing Without CDB HDR MEAS To rectify this issue the input signal can be amplified in this case by 13 3 dB This will also amplify the noise floor however since the noise floor is small compared to the signal the signal will dominate the amplification In the figure below the signal and noise floor have been shifte...

Page 21: ... setting up and configuring Cirrus Logic devices and software The following sections show how to use WISCE software to configure and test CS43131 and using the CDB43131 board and the CDB43131 Board 5 1 Launching WISCE Software Click on the Start Button All Programs Wolfson Evaluation Software and select WISCE V3 to launch the WISCE software Figure 18 Launch WISCE ...

Page 22: ...which is an IO Expander The device at address 0x60 is CS43131 CSP DUT and the device at address 0x62 is the CS43131 QFN DUT Figure 19 Found Devices 5 2 Loading the CDB43131 board Panel and Register Map To load the CDB43131 board panel and register map double click on the Unknown device at address 0x44 to launch Change Device pop up window Alternatively the Change Device pop up window can also be l...

Page 23: ...CDB43131 GBK DS1155V2DB1 23 Click Accept to load the CDB43131 board Panel and Register Map shown in the following figures Figure 21 TCA6424 Panel Figure 22 TCA6424 Register Map ...

Page 24: ... pop up window by either double clicking on Unknown Device or right clicking on Unknown Device at address 0x60 and selecting Properties Select CS43131 Rev A1 from the Device drop down menu and click Accept to load the plugin and register map for the CS43131 Figure 23 Select CS43131 CSP Figure 24 Select CS43131 QFN Figure 25 CS43131 Register Map ...

Page 25: ...CDB43131 GBK DS1155V2DB1 25 To view CS43131 plugin click on Tuning and select CS43131_Plugin Figure 26 CS43131 Plugin ...

Page 26: ...he CDB43131 Board The following steps show how to detect the presence of the CS43131s on the CDB43131 Board 1 Under the CDB431XX_I2C_GPIP_EXP menu click on QUICK_START and click CDB_INIT txt This will reset the board into a default mode Figure 27 Initialize DACs ...

Page 27: ...be each tab and its function The user can configure the CS43131 using these tabs However it is recommended that the user initially use the profile scripts that are provided with the plugin to configure and control the CS43131 since each field will be preconfigured correctly for the proper mode 5 5 1 Main Tab This tab shows the block diagram of the internal architecture of the CS43131 Figure 28 Mai...

Page 28: ...1 GBK 28 DS1155V2DB1 5 5 2 Sys_Config Tab This tab allows user to configure the CS43131 clock input settings It also allows the user to configure CLKOUT and Class H amplifier settings Figure 29 Sys_Config Tab ...

Page 29: ...rface by clicking on the Power Down XTAL LED LED color will change to Red 4 Click on XTAL Status button If Ready LED is lit the crystal Interface has been configured successfully and the CS43131 is ready to use XTAL as MCLK source Go to step 6 5 If Error LED is lit then the crystal interface is not configured Power down the board Check the crystal and the crystal circuit on the board 6 Select XTAL...

Page 30: ...CDB43131 GBK 30 DS1155V2DB1 5 5 3 PLL Tab This tab allows the user to configure the CS43131 PLL The PLL can be used as an alternate source for the CS43131 MCLK Figure 31 PLL Tab ...

Page 31: ...eadphone impedance measurement Figure 32 Headphone Tab 5 5 4 1 Enabling Headphone Output The following steps show how to enable the headphone output using the Headphone tab 1 Enable headphone interrupts by checking the Enable Headphone Interrupts check box 2 Configure MCLK source Configure audio input port 3 Power up headphone by checking the Enable Headphone Output check box 4 The headphone outpu...

Page 32: ...hrough 1 Connect audio output from a source to the HPIN jack on the CDB43131 board 2 If the CS43131 is coming out of reset enable analog audio passthrough by checking the External HP Input check box Else skip to step 3 3 Disable the headphone output if it is not already disabled 4 Enable analog audio passthrough by checking the External HP Input check box 5 5 4 4 Headphone Presence Detection The f...

Page 33: ...ent 1 Set XTAL as MCLK source 2 Power down headphone if not already powered down 3 Enable impedance interrupts by checking Enable Impedance Interrupts check box 4 Enable impedance subsystem by checking Enable Impedance Subsystem check box 5 If the ON Status LED turns green then the impedance subsystem is enabled Proceed to step 5 Else the impedance subsystem did not get enabled Power cycle the boa...

Page 34: ...d be measured before measuring AC Impedance 1 Enter the frequency at which the impedance should be measured into Frequency box 2 Click the Left Channel button to start AC impedance measurement for the left channel 3 Once the impedance measurement is complete the measured impedance will be displayed in ohms 4 Click the Right Channel button if AC impedance measurement of right channel is desired Fig...

Page 35: ...Sweep check box This will load AC frequency sweep controls 2 Enter the Start Frequency Stop Frequency and the of Points 3 Click the Start button next to Left Channel to start AC impedance sweep for left channel and real time plotting 4 Click the Start button next to Right Channel to start AC impedance sweep for right channel and real time plotting 5 To save left channel sweep data click Save Left ...

Page 36: ...K 36 DS1155V2DB1 5 5 5 ASP Config Tab This tab allows the user to configure the ASP port The following figure shows ASP Config tab contents when ASP is configured to operate in Slave mode Figure 36 ASP Config Tab ...

Page 37: ...CDB43131 GBK DS1155V2DB1 37 The following figure shows the contents of ASP Config tab when ASP is configured to operate in Master mode Figure 37 ASP Config Tab in Master Mode ...

Page 38: ...nal MCLK MCLK_INT and the values in ASP Numerator ASP Denominator LRCLK high Time and LRCLK Period text boxes The value in the LRCLK Frequency text box will be used to set the new sample rate if it is not already set by user when the ASP is powered up Figure 38 Calculating ASP Clock Frequencies It is recommended to use a profile script to configure this port since each field will be preconfigured ...

Page 39: ...5V2DB1 39 5 5 6 XSP Config Tab This tab allows the user to configure the XSP port The following figure shows XSP Config tab contents when XSP is configured to operate in Slave mode Figure 39 XSP Config Tab in Slave Mode ...

Page 40: ...CDB43131 GBK 40 DS1155V2DB1 The following figure shows the contents of XSP Config tab when XSP is configured to operate in Master mode Figure 40 XSP Config Tab in Master mode ...

Page 41: ...nal MCLK MCLK_INT and the values in XSP Numerator XSP Denominator LRCLK high Time and LRCLK Period text boxes The value in the LRCLK Frequency text box will be used to set the new sample rate if it is not already set by user when the XSP is powered up Figure 41 Calculating XSP Clock Frequencies It is recommended to use a profile script to configure this port since each field will be preconfigured ...

Page 42: ... This tab allows the user to change PCM filter dynamically during playback The impulse and magnitude responses of the selected filter are displayed It is recommended to use a profile script to configure this part since each field will be preconfigured correctly for the proper mode Figure 42 PCM Playback Tab ...

Page 43: ...B43131 GBK DS1155V2DB1 43 5 5 8 DSD Playback Tab This tab allows the user to configure the DSD DoP playback path It is recommended to use a profile script to configure this port Figure 43 DSD Playback Tab ...

Page 44: ...DSD Speed yyy is the output voltage level DSD through XSP header J26 DoP Playback 64fs Mode Slave CDB_PCM_In_Ext_Slave DoP_DSD64_playback_XTAL_Slave PCM through ASP header J25 CDB_Spdif_In_Clk_External DoP_DSD64_playback_XTAL_Slave S PDIF J10 CDB_Coax_In_Clk_External DoP_DSD64_playback_XTAL_Slave Coaxial J11 DoP Playback 128fs Mode Slave CDB_PCM_In_Ext_Slave DoP_DSD128_playback_XTAL_Slave PCM thro...

Page 45: ...CDB43131 GBK DS1155V2DB1 45 6 1 Data Flow for Various Use Cases The following sections depict the flow of data in red for various common use cases 6 1 1 PCM Playback Figure 44 PCM Playback Data Flow ...

Page 46: ...CDB43131 GBK 46 DS1155V2DB1 6 1 2 DSD Playback Figure 45 DSD Playback Data Flow ...

Page 47: ...CDB43131 GBK DS1155V2DB1 47 6 1 3 Analog Audio Playback Figure 46 Analog Audio Playback Data Flow ...

Page 48: ...sure that the CDB4131 jumpers are set to factory default mode 1 Power up the CDB43131 by applying 5 V or VBUS through a USB connection 2 Connect a cable from Digital Serial IO Transmitter port of an APx e g APx555 to header J25 on CDB43131 board There is no need to connect the MCLK signal 3 Follow the steps described in the Quick Setup Guide to launch WISCE software and load plugins 4 Load the pro...

Page 49: ...nfigure the APx for running the tests This procedure was tested using an APx555 1 Run the APx software APx500 v4 2 if using an APx555 2 Set the APx Output to Digital Serial and Input to Analog Balanced 3 Set the Input Bandwidth to 20 Hz to 22 4 kHz Figure 48 APx Signal Path Setup ...

Page 50: ...3131 GBK 50 DS1155V2DB1 4 In the Signal Path Setup panel click on the settings button next to Connector drop down menu and configure Digital Serial Settings as shown below Figure 49 Digital Serial Settings ...

Page 51: ... GBK DS1155V2DB1 51 5 To launch the Dynamic Range Measurement test click on Project Add Measurement Meters Dynamic Range AES17 This will launch the dynamic range test screen Figure 50 Launch Dynamic Range Test ...

Page 52: ...1 6 To run the Dynamic Range Measurement test configure the Input Level and Bandwidth as shown below Click on the Start button to run the test Dynamic Range values will be displayed for both channels Figure 51 Dynamic Range Test ...

Page 53: ...CDB43131 GBK DS1155V2DB1 53 7 To launch THD N test click on Project Add Measurement Meters THD N to launch THD N measurement window Figure 52 Launch THD N Test ...

Page 54: ...s shown below Click on the Generator button to run the test THD N ratio will be displayed for both channels THD N ratio is typically displayed in Percentage To display the values in dB select dB from the drop down menu next to Unit on top of the display Figure 53 THD N Measurement Settings ...

Page 55: ...h the CDB HDR MEAS board 6 2 3 1 Measuring Dynamic Range The following steps show the procedure to measure dynamic range 1 Place a jumper connecting the 600 Ω load on J15 2 Place a jumper connecting the 600 Ω load on J4 3 Connect a headphone cable between CSP HPOUT J1 and the input of the CDB HDR MEAS 4 Power up the CDB HDR MEAS board with 15V and GND 5 For each channel connect a cable between the...

Page 56: ...back in Slave Mode 6 2 4 1 Measuring THD N on CSP Device The following steps show the procedure to measure THD N 1 Place a jumper connecting the 600 Ω load on J15 2 Place a jumper connecting the 600 Ω load on J4 3 Connect a headphone RCA or headphone BNC cable between CSP HPOUT J1 and the Balanced port on Analog inputs 1 and 2 on the APx Figure 55 THD N Measurement for CS43131 CSP 4 Configure APx ...

Page 57: ... N 1 Place a jumper connecting the 600 Ω load on J17 2 Place a jumper connecting the 600 Ω load on J31 3 Connect a XLR cable between QFN OUT J60 and the Balanced XLR port on Analog input 1 on the APx Figure 56 THD N Measurement for CS43131 QFN 4 Configure APx and run THD N Measurement test as described in section 6 2 2 ...

Page 58: ...N Results Output Load RL Full Scale Voltage VRMS Channel Datasheet Spec Typical Measured Result 1 600 1 7 A 113 dB 113 0 dB B 113 2 dB XLR 114 1 dB 32 1 0 A 110 dB 108 5 dB B 107 7 dB XLR 111 8 dB 16 0 5 A 100 dB 103 8 dB B 103 5 dB XLR 108 8 dB Notes 1 Refer to the CS43131 data sheet for test conditions 6 3 3 Dynamic Range Results The table below lists measured DNR results using the test waveform...

Page 59: ...CDB43131 GBK DS1155V2DB1 59 7 Revision History Revision Changes DB1 JUL 18 Initial release ...

Page 60: ...LLY AT THE CUSTOMER S RISK AND CIRRUS LOGIC DISCLAIMS AND MAKES NO WARRANTY EXPRESS STATUTORY OR IMPLIED INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE WITH REGARD TO ANY CIRRUS LOGIC PRODUCT THAT IS USED IN SUCH A MANNER IF THE CUSTOMER OR CUSTOMER S CUSTOMER USES OR PERMITS THE USE OF CIRRUS LOGIC PRODUCTS IN CRITICAL APPLICATIONS CUSTOMER AGREES BY SUCH U...

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