CDB4271
5
1.4
Canned Oscillator
Oscillator Y1 provides a System Clock (OMCK) to the CS8416. This clock can be routed
through the CS8416 and out the RMCK pin by simply disconnecting the S/PDIF input. To use
the canned oscillator as the source of the MCLK signal, configure the board to receive MCLK
from the CS8416 using either the MCLK[1:0] positions on S1 or the GUI, and remove the
input S/PDIF stream. Care should be taken to ensure that the crystal (Y2) is removed when
the board is configured to receive MCLK from the canned oscillator.
The oscillator is mounted in pin sockets, allowing easy removal or replacement. The board is
shipped with a 12.000 MHz crystal oscillator stuffed at Y1. Please refer to the CS8416 data
sheet for details on OMCK operation.
1.5
Analog Input
RCA connectors supply the CS4271 analog inputs through unity gain, AC-coupled single-
ended circuits. A 1 Vrms single-ended signal will drive the CS4271 inputs to full scale.
The CDB4271 was designed for use with not only the CS4271, but also the CS4272 with a
simple change of assembly options. For this reason, the input buffer schematic shown in
Figure 8 reflects only the configuration assembled on the CDB4271. For a complete sche-
matic of the analog input buffer printed on the PCB, refer to the CDB4272 data sheet
1.6
Analog Outputs
The CS4271 analog output is routed through a differential to single-ended, unity-gain low
pass filter, which is AC-coupled to an RCA phono jack (see Figure 9). The analog output filter
on the CDB4271 has been designed to add flexibility when evaluating the CS4271 DAC out-
puts. The output filter was designed in a two stage format, with the first stage being an op-
tional instrumentation amplifier, and the second stage a 2-pole butterworth low pass filter.
The 2-pole low pass filter provides an example of an inexpensive circuit with good distortion
and dynamic range performance. It is designed to have the in-band impedance matched be-
tween the positive and negative legs. It also provides a balanced to single-ended conversion
for standard un-balanced outputs. Evaluate this circuit by placing the FILT jumpers (three per
output channel) to position 1 (selectable by J13, J14 & J15 for AOUTR, etc.).
The instrumentation amplifier is optionally inserted before the LPF by changing the FILT
jumpers to position 2. The instrumentation amplifier incorporates a 5x gain (+14 dB) which
effectively lowers the noise contribution of the following 2-pole LPF. This improves the overall
dynamic range of the system. The gain of this stage is determined from the
following equation:
Gain
1
2 R
( )
R2
------------
+
=
Summary of Contents for CDB4271
Page 16: ...CDB4271 16 5 SCHEMATICS AND LAYOUT Figure 6 Hierarchy Schematic Sheet 1 ...
Page 17: ...CDB4271 17 Figure 7 CS4271 Schematic Sheet 2 ...
Page 18: ...CDB4271 18 Figure 8 Analog Input Schematic Sheet 3 ...
Page 19: ...CDB4271 19 Figure 9 Analog Output Schematic Sheet 4 ...
Page 20: ...CDB4271 20 Figure 10 CS8416 S PDIF Receiver Schematic Sheet 5 ...
Page 21: ...CDB4271 21 Figure 11 CS8406 S PDIF Transmitter Schematic Sheet 6 ...
Page 22: ...CDB4271 22 Figure 12 Board Setup Schematic Sheet 7 ...
Page 23: ...CDB4271 23 Figure 13 PCM Header Schematic Sheet 8 ...
Page 24: ...CDB4271 24 Figure 14 Control Port Schematic Sheet 9 ...
Page 25: ...CDB4271 25 Figure 15 Power Schematic Sheet 10 ...
Page 26: ...CDB4271 26 Figure 16 Component Placement and Reference Designators ...
Page 27: ...CDB4271 27 Figure 17 Top Layer ...