DSB75 Development Support Board Rev. B1 Hardware Description
Confidential / Released
DSB75_hd_v12
Page 46 of 96
2008-08-26
V500/
V501
S500,
S501
1
3
I2CCLK,
I2CDAT
I2C_CLK_5V,
I2C_DAT_5V
I2C_CLK_3V,
I2C_DAT_3V
VDD
5V
0
3k3
3k3
VDD
A(0:2)
SCL,SDA
S502 (A0),
S503 (A1),
S504 (A2)
EEPROM
128kBit
D500
3
1
AT24C128N
1,3
2,4
level shifter:
Address
8,10
5V0
VDD
7
9
5V0
VDD
X511
GND
11,70
X100
B2B
10 pole pin
2
3
V504 (DAT)
V503 (CLK)
0=on
1=off
VDD
2
2
2
2
Figure 23: I²C interface
S504
S503
S502
S501
S500
X511
1
2
9
10
V504
V503
Figure 24: I²C interface location