20
Pin Function Descriptions
Pin(s) Name
Function
90 RX0+
TMDS Low Voltage Differential Signal input data pairs
91 RX0-
TMDS Low Voltage Differential Signal input data pairs
85 RX1+
TMDS Low Voltage Differential Signal input data pairs
86 RX1-
TMDS Low Voltage Differential Signal input data pairs
80 RX2+
TMDS Low Voltage Differential Signal input data pairs
81 RX2-
TMDS Low Voltage Differential Signal input data pairs
93 RXC+
TMDS Low Voltage Differential Signal input clock pair.
94 RXC-
TMDS Low Voltage Differential Signal input clock pair.
49 56 QO0 QO7
8bit odd-pixel Blue output
59 66 QO8 QO15
8bit even-pixel Green output
69 75,77 QO16 QO23
8bit odd-pixel Red output
10 17 QE0 QE7
8bit even -pixel Blue output
20 27 QE8 QE15
8bit even -pixel Green output
30 37 QE16 QE23
8bit even -pixel Red output
99 RESERVED
Must be tied HIGH for normal operation.
100 OCK_INV
ODCK Polarity. A LOW level selects normal ODCK
output. A HIGH level selects inverted ODCK output.
1 HS_DJTR
This pin enables/disable the HSYNC dejitter function.
To enable the HSYNC function this pin should be tied
high. To
2 PD
Power Down (active LOW). A HIGH level indicates
normal operation. A LOW level indicates power down
mode.
3 ST
Output Drive. A HIGH level selects HIGH output drive
strength. A LOW level selects LOW output drive
strength.
4 PIXS
Pixel Select. A LOW level indicates one pixel (up to
24-bits) per clock mode using QE[23:0]. A HIGH level
indicates two pixels (up to 48-bits) per clock mode
using QE [23:0] for first pixel and QO[23:0] for second
pixel.
7 STAG_OUT
Staggered Output. A HIGH level selects normal
simultaneous outputs on all odd and even data lines.
A LOW level selects staggered output drive.
8 SCDT
Sync Detect. A HIGH level is outputted when DE is
actively toggling indicating that the link is alive. A
LOW level is outputted when DE is inactive, indicating
the link is down.
9 PDO
Output Driver Power Down (active LOW). A HIGH
level indicates normal operation. A LOW level puts all
the output drivers only (except SCDT and CTL1) into
a high impedance (tri-state) mode.
44 ODCK
Output Data Clock. This output can be inverted using
the OCK_INV pin.
46 DE
Output Data Enable.
47 VSYNC
Vertical Sync input control signal.
48 HSYNC
Horizontal Sync input control signal.
18,29,43,57,78 OVCC
Output VCC
19,28,45,58,76 OGND
Output GND
6,38,67 CVCC
Digital Core VCC,
5,39,68 GND
Digital Core GND.
82,84,88,95 DAVCC
Analog VCC