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Changhong Electric PT4206 Service Manual Download Page 17

17 

 

2.2.

5 TA2024 general: 

The TA2024 is a 10W/ch continuous average two-channel Class-T Digital Audio Power 

Amplifier IC using Tripath’s proprietary Digital Power Processing™ technology. Class-T 

amplifiers offer both the audio fidelity of Class-AB and the power efficiency of Class-D 

amplifiers. 

Pin Function Descriptions

 

Pin(s) Name 

Function 

2, 3 

DCAP2, DCAP1 

Charge pump switching pins 

4, 9 

V5D, V5A 

Digital 5VDC, Analog 5VDC 

5, 8, 17 

AGND1, AGND2, AGND3 

Analog Ground 

6 

REF 

Internal reference voltage 

7 

OVERLOADB 

A logic low output indicates the input signal 
has overloaded the amplifier 

10 14 

OAOUT1, OAOUT2 

Input stage output pins. 

11, 15 

INV1, INV2 

Single-ended inputs 

12 MUTE 

Mute 

control 

16 

BIASCAP 

Input stage bias voltage 

18 

SLEEP 

Sleep mode control 

19 

FAULT 

A logic high output indicates thermal 
overload 

20, 35 

PGND2, PGND1 

Power Grounds (high current) 

22 DGND 

Digital 

Ground 

24, 27; 31, 28 

OUTP2  &  OUTM2;  OUTP1 
& OUTM1 

Bridged outputs 

25, 26, 29, 30 

VDD2, 

VDD2

VDD1, 

VDD1 

Supply pins for high current H-bridges, 
nominally 12VDC. 

13, 21, 23, 32, 34  NC 

Not connected 

33 VDDA 

Analog 

12VDC 

36 

CPUMP 

Charge pump output   

1 

5VGEN 

Regulated 5VDC source used to supply 
power to the input section (pins 4 and 9). 

Summary of Contents for PT4206

Page 1: ...1 PDP TELEVISION SERVICE MANUAL MODEL NO PT4206 Please read this manual carefully before service ...

Page 2: ...rt Introduction on Circuit Functions of PT4206 Part Analysis on Signal Process of PT4206 Part Typical Defectives and Repair of PT4206 Annex 1 Main Assembly Drawing of PT4206 2 Wire Connecting Drawing of PT4206 Part PP06 Chassis Features and CBU Contents ...

Page 3: ...ain Features 1 2 1 Terminals RF Input 1 Rear S Terminal Input 1 Rear Recommended Input Format 640Ў Б 480 60Hz 800Ў Б 600 60Hz Unsupportable Input Format Indication Yes Color Temp Adjust Yes Quick Plug In Use Yes PC Picture Location Adjust Yes HD Signal Ј Ё YPbPrЈ Compatible with 480PЎў 576PЎў 720P Ўў 1080i HD Signal Ј Ё DVIЈ Compatible with 480PЎ ў 576PЎ ў 720P Ўў 1080i and HDTV Picture System PAL...

Page 4: ...lish Menu Location movable by user Blue Background without Signal Yes Power Saving When TV is connected with PC input while there is no signal from PC after 60 seconds TV will be automatically off and enter into Power Saving Mode Press any key on TV or R C or there is signal from PC again TV will be switched on automatically Pixel Movement When this function is on pictures will move on regularly t...

Page 5: ...binet Filter Glass Shelve Bar PDP Panel Module Down Cover Module etc Back Cabinet Remarks This drawing is for references only please see the main assembly diagram and wire connecting diagram for details 1 3 2 Circuit Content ...

Page 6: ...gulating Circuit RF Circuit VGA Analog Video Digital Video Signal Processing Circuit System Control Circuit Button Control Circuit Reference drawing as below Part Introduction on Circuit Functions of PT4206 2 1 Changhong PDP TV PT4206 main IC functions ...

Page 7: ...lity of up to 140 MHz it can accurately support display resolutions up to 1280x1024 SXGA at 75 Hz The clamped input circuits provide sufficient bandwidth to accurately digitize each pixel The MST9885B provides a high performance highly integrated solution to support the digitization process including the ADCs a voltage reference a PLL to generate the pixel sampling clock from HSYNC clamping circui...

Page 8: ...put 49 SOGIN Sync on Green analog input 48 GAIN Green analog input 54 RAIN Red analog input 29 COAST Hold PLL frequency and do not track HSYNC 38 CLAMP External clamp input we connect it to ground 55 A0 Serial interface address pin 56 SCL I2 C bus clock 57 SDA I2 C bus data 33 FILT PLL connect to external filter 26 27 39 42 45 46 51 52 59 62 AVDD Analog power 11 22 23 69 78 79 V33 Digital output p...

Page 9: ...ck Output 27 LLC2 Clock Output 28 LLC1 NC 31 34 37 40 Y0 Y7 YUV signal output Digital ITU R656 format 41 44 47 50 C0 C7 Digital chromatic signal output 53 INTLC Interlace scan control output 0 odd 1 even 54 AVO Active Video Output 55 FSY HC NC 56 MSY HS Horizontal Sync Pulse output 57 VS Vertical Sync Pulse 58 FPDAT NC 60 CLK5 5 MHz Clock Output 61 NC NC 62 XTAL1 20 25M Analog Crystal Input 63 XTA...

Page 10: ...rts sophisticated bit mapped based OSDs The OSD controller supports transparent translucent and fade in fade out functions Pin Function Descriptions Pin s name Function Video Port Pin Descriptions 71 VCLK VPort Pixel Clock input 74 VVS VPort Vertical Sync input 75 VHS VPort Horizontal Sync input 69 VFIELD VGPort Field Input 70 VPEN VPort Pixel Enable 47 56 YUV0 YUV7 VGPort ITUR656 Pixel Data I O p...

Page 11: ...er devices 196 ROMOE ROM Output Enable low output indi cates a read from external ROM 197 ROMWE ROM Write Enable low indicates a write to external ROM 198 CS0 Chip select signal 199 CS1 Chip select signal 193 NMI Non maskable Interrupt 164 173 184 187 192 A1 A19 Microprocessor address bus output bits 148 163 D0 D15 Microprocessor 16 bit bidirectional data bus Peripheral Interface Pin Descriptions ...

Page 12: ...04 123 140 171 208 VDDQ3 3 3V digital I O power 1 30 53 73 87 105 124 141 172 VSSQ Digital I O ground 165 VDDPA2 1 8V analog clock generator power 166 VSSPA2 Clock generator analog ground 167 VDDPA1 1 8V analog clock generator power 168 VSSPA1 Clock generator analog ground PW113 Block Diagram 2 2 4 PW1235 General PW1235 supports standard digital video signal incorporates deinterlacing ...

Page 13: ...l Graphics DG port vertical sync 66 DGHS Digital Graphics DG port horizontal sync 91 92 94 95 97 100 DGR0 DGR7 Digital Graphics DG port red data 81 84 86 89 DGG0 DGG7 Digital Graphics DG port green data 70 73 75 76 78 79 DGB0 DGB7 Digital Graphics DG port blue data Analog Display Port Pin Descriptions 156 ADR Analog display port red V Pr data 153 ADG Analog display port green Y Y data 150 ADB Anal...

Page 14: ...s bus 190 MCUCS Chip select 191 MCUWR MCUR W signal 192 MCUCMD MCU command signal 188 MCURDY MCU Ready signal Miscellaneous Pin Descriptions 56 TEST Test mode 144 TESTCLK Used for testing can be used to supply display clock 55 RESETn Hardware asynchronous reset 40 XTALI Crystal oscillator input 41 XTALO Crystal oscillator output 146 CGMS CGMS Enable 201 MVE Macrovision write protected enable 62 63...

Page 15: ...og power 3 3V for G Y Y channel 151 AVD33B Analog power 3 3V for B U Pb channel 158 AVS33R Analog ground for R V Pr channel 155 AVS33G Analog ground for G Y Y channel 152 AVS33B Analog ground for B U Pb channel 163 ADAVDD Analog power supply 2 5V for the analog display port 164 ADAVSS Analog ground for the analog display port 149 ADDVDD Digital power supply 2 5V for the analog display port 148 ADD...

Page 16: ...16 PW1235 Block Diagram ...

Page 17: ...tage 7 OVERLOADB A logic low output indicates the input signal has overloaded the amplifier 10 14 OAOUT1 OAOUT2 Input stage output pins 11 15 INV1 INV2 Single ended inputs 12 MUTE Mute control 16 BIASCAP Input stage bias voltage 18 SLEEP Sleep mode control 19 FAULT A logic high output indicates thermal overload 20 35 PGND2 PGND1 Power Grounds high current 22 DGND Digital Ground 24 27 31 28 OUTP2 O...

Page 18: ...nd 3 bits of LCD timing and control data FPLINE FPFRAME DRDY are transmitted at a rate of 455 Mbps per LVDS data channel Using a 65 MHz clock the data throughput is 227 Mbytes sec The DS90C383A transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin The DS90CF383A is fixed as a Falling edge strobe transmitter Pin Function Descriptions Pin s Name Function...

Page 19: ...al technology to support high resolution displays up to UXGA The Sil161B receiver supports up to true color panels 24 bit pixel 16 7M colors in 1 or 2 pixels clock mode In addition the receiver data output is time staggered to reduce ground bounce that affects EMI All Panel Link products are designed on a scaleable CMOS architecture This ensures support for future performance requirements while ma...

Page 20: ...ower Down active LOW A HIGH level indicates normal operation A LOW level indicates power down mode 3 ST Output Drive A HIGH level selects HIGH output drive strength A LOW level selects LOW output drive strength 4 PIXS Pixel Select A LOW level indicates one pixel up to 24 bits per clock mode using QE 23 0 A HIGH level indicates two pixels up to 48 bits per clock mode using QE 23 0 for first pixel a...

Page 21: ...log VCC 97 PVCC PLL Analog VCC 98 PGND PLL Analog GND 96 EXT RES Impedance Matching Control In the common case of 50Ω transmission line an external 390Ω resistor must be connected between AVCC and this pin SiI161B Block Diagram ...

Page 22: ...nd 5 V PLL power supply Moreover 5 and 6 pin of N901 switch the Color system sending out from 44 and 50 pin of PW113 10 pin of N901 outputs video signal follows to Q905 through the video switch circuit switching with the AV S VIDEO Input signal after them disposal in VPC3230 3 1 1 2 SOUND Disposal the 9 pin of N901 outputs the second sound IF signal enlarged by the Q910 following to Q602 and passi...

Page 23: ...n of TEA6425D and other channel S video signal Y C signal sends to 6 5 pin of TEA6425D respectively The three signals switches in the TEA6425D VIDEO or Y signal outputs toVPC3230D from 17pin C signal outputs from 18pin at the same time 19 pin video outputs from19 pin VPC3230 The signal from TEA6425 after switch and A D send to chroma decode circuit which can identify PAL NTSC SECAM signal automati...

Page 24: ...ation outputs digital signal correctly VGA signal video signal DVI signal after digital disposal sends to video format disposal ic PW113 to change the video format outputs the digital R G B signal which fits PDP display driver PW113 the input video signal after disposalled by PW113 outputs 852 480 resolution digital R G B signal which fits PDP panel spec and relevant sync clock signal and transfor...

Page 25: ...35 I channel SV Digital video and clock PW113 SCALER DS90C383 D LVDS SDRAM B U E RF MSP3410G FmorNICAM demodulation SRS WOW sound 67 SIF TA2024 sound amplifier 27 28 S0 S1 PW1235E LVDSON Main control signal 1 RST1 High enable 2 STANBY control Low is power ON 3 MUTE high mute 4 sound switch S0 S1 5 PW1235Econtrol High enable BUFFER and polarity controlled by Q3 6 LVDSON control MUTE SO S1 D K 1 0 B...

Page 26: ...decode Not NTSC NTSC switch by bus 16 uPD64083 comb filter 88 NTSC Sync separate 83 84 73 71 Y C PW1235 I channel SV Digital video and clock PW11 SCALER DS90C38 D LVDS output SDRA B E MSP3410 Sound switch SRS WOW sound disposal 53 TA2024 sound amplifier 27 28 PW1235 LVDSO MUT E 54 L R ...

Page 27: ...eo switch 17 Y VPC3230 decode PW1235 I channel SV Digital video and clock PW11 SCALER DS90C38 D LVDS output SDRA B U E MSP3410 Sound switch SRS WOW sound disposal 53 TA2024 sound amplifier 27 28 PW1235 LVDSO MUT 54 L R 5 C 74 18 72 C ...

Page 28: ...TSC When NTSC switch video signal 16 uPD64083 comb fliter 88 NTSC video Sync separate 83 84 73 71 Y C PW1235 I channel SV Digital video and clock PW11 SCALER disposal DS90C38 D LVDS output SDRA B E MSP3410 Sound switch SRS WOW sound disposal 53 TA2024 sound amplifier 27 28 PW1235 LVDSO MUT E 54 L R ...

Page 29: ...switch AD9883 G PW113 Format identify PW113 SCALER DS90C383 D LVDS output B U E Pr MSP3410 Sound switch SRS WOW sound disposal 47 TA2024 sound amplifier 27 28 Y Pb PW1235 LVDSO MUT VGASE 5 11 2 1 4 7 9 54 48 43 R G B 48 L R ...

Page 30: ...h SRS WOW sound disposal 50 TA2024 sound amplifier 27 28 R G PW1235 LVDSO Main control signal 1 RST1 High enable 2 STANBY control Low is power ON 3 MUTE High mute 4 VGASEL control High enable 5 PW1235E control High enable BUFFER and polarity are controlled by Q3 6 LVDSON control MUT VGASE 3 6 10 1 13 HS 12 4 7 9 54 48 43 R G B 31 U9 VS BUF ER PW1235 Not standard mode adjust AD9883 switch the chann...

Page 31: ... work normally MST9885 VPC3230 SiI161B DS90CF383 take proper power supply Moreover LED signal control LED to turn yellow and glitter it is said that it controls normally At last LVDSON signal from 43pin of PW113is high it let DS90CF383 begin to work After this it is in normal work state input source is last time source before power off SiL161 G PW113 Format identify PW113 SCALER vertical sync 60HZ...

Page 32: ... in normal work state when video signal inputs PDP panel display normally if no video signal input under the control of PW113 PDP panel displays blue background if no signal 15 mins power off automatically and into standby state It can not arouse automatically 3 3 3 When in DVI digital RGB mode by remote device PW113 controls SiI161B and enables VPC3230 and let it working in low consume mode other...

Page 33: ...ard connect U 20 M A X 202E U 16 P W 113 16Ў ў 37Ў ў 65Ў ў 84Ў ў 137Ў ў 185pi n V LL N K 605 rem ot e head V D K 1 LE D U 16 P W 113 165Ў ў 167pi n V P P U 17 29LV 800B 37pi n U 19 24LC 32 8pi n U 16 P W 113 29Ў ў 52Ў ў 72Ў ў 86Ў ў 104Ў ў 123Ў ў 140Ў ў 171Ў ў 208pi n V U U 3 4 2 2 D6V power branch ...

Page 34: ...D 9883A 26Ў ў 27Ў ў 39Ў ў 42Ў ў 45Ў ў 46Ў ў 51Ў ў 52Ў ў 59Ў ў 62 pi n V FF U 6 A D 9883A 34Ў ў 35 pi n V E E V C C U 28 LM 1086C S X 2 5 U 3 P W 1235 5Ў ў 34Ў ў 93Ў ў 123Ў ў 140Ў ў 175Ў ў 205Ў ў 235 pi n V X X U 3 P W 1235 197Ў ў 199 pi n V Y Y U 3 P W 1235 58Ў ў 60 pi n V ZZ U 3 P W 1235 149Ў ў 163Ў ў 166 pi n Ј 2 5 ...

Page 35: ...ў 256pi n U 3 P W 1235 51Ў ў 54Ў ў 57pi n U 22 D C 90C 383 1Ў ў 9Ў ў 26pi n U 10 U 12 U 14 U 15 74LV C 16244 7Ў ў 18Ў ў 31Ў ў 42 pi n U 22 D C 90C F383 34pi n U 22 D C 90C F383 44pi n U 6 A D 9883 11Ў ў 22Ў ў 23Ў ў 69Ў ў 78Ў ў 79pi n U 71 74LV 32 14pi n U 1 V P C 3230 10Ў ў 29Ў ў 36Ў ў 45Ў ў 52pi n t o reduce i nt erf erenceЈ U 11 pow er i s di vi ded i nt o V D D Ў ў V I I Ў ў V JJ by LC f i l t ...

Page 36: ... 11pi n 5V TU N E R TV vi deoЎ ў S I F f ol l ow am pl i f er ci rcui t N 702 LM 1117 2 5 N 703 LM 1117 3 3 5V 2 N 701 i nput vi deo and out put Y C f i l t er am pl i f er ci rcui t 5V 3D U 701 uP D 64083 53Ў ў 81Ў ў 92Ў ў 93pi n A 2 5V N 701 uP D 64083 31Ў ў 32Ў ў 45Ў ў 46Ў ў 64Ў ў 100pi n D 2 5V N 701 uP D 64083 38pi n D 3 3V N 701 sm al l si gnal f i l t er am pl i f er ci rcui t ...

Page 37: ...37 3 4 2 5 A12Vpower branch X P 805 3pi n N 651 TA 78M 08 P C Y P bP r sound am pl i f er 8V N 902 TE A 6425D 20pi n N 601 M S P 3410G 39pi n A V O U T sound am pl i f er ...

Page 38: ...1 2 pin 5V power supply Check mainboard jack XP801 2 pin 5V power Check resistance RK2 LBD VDK1 Check K board iack XK01 11 pin 5V power Check power filter and power jack AC 220V input 1 Check XP801 2 pin short circuit to ground whether or not 2 Check mainboard L801 3 Check PW113 reset circuit clock circuit Check circuit connect ...

Page 39: ...nce 2Ў ў checkN 803Ў ў N 804 N o check X 3 14 318M cryst al Y es N o change Y 2 cryst al check P W 113 R E S E T pi n vol t age Y es check reset ci rcui t N o check A M 29LV 800B T t o P W 113 addressЎ ў dat aЎ ў cont rol Y es change A M 29LV 800B T or P W 113 and w i re bet w een t hem I 2C bus 1Ў ў check V P C 3230Ў ў P W 1235 pow er ci rcui t 2Ў ў check V P C 3230Ў ў P W 1235 reset vol t age 3Ў...

Page 40: ...k t he l i ne N o Y es m end check LV D S si gnal N o 1Ў ў LV D S O N i s hi gn or not 2Ў ў check P W 113 syncЎ ў pi xel cl ockЎ ў R G B dat a si nal N o checkD S 90c383 pow er suppl y Y es check P W 113 out put port Ј change P W 113 N o check pow er suppl y N o check D S 90C 383Ј change Y es check P W 113 syncЎ ў pi xel cl ockЎ ў R G B dat a si nal Y es check cryst al f requent Ј check P W 113Ј c...

Page 41: ...abnorm al i t y check sync f ace l i f t i ng ci rcui t and peri pheral l y ci rcui t out put abnorm al i t y no pi ct ure onl y D V I check S i I 161B 169 Ј Ё 44Ј Ј Ё 48Ј Ј Ё 47Ј Ј Ё 42Ј pi n G C LK Ў ў G H S Ў ў G V S Ў ў G FB K checkS i I 161B 169 cont rol si gnal al l abnorm al i t y 1Ў ў check si gnal source 2Ў ў D V I j ack 3Ў ў change S i i 161B part abnorm al i t y ot her part i s f ol l o...

Page 42: ...e V P C 3230 check and change P W 1235 Y es N o repai r abnorm al i t y check A V board connect or check TE A 6425D I O j oi nt w el l check TE A 6425 pow erЎ ў busЈ change TE A 6425 i nput w el l but out put bad check TE A 6425D 14 pi n vi deo out out check uP D 64083 reset Ў ў cl ockЎ ў pow erЈ changeuP D 64083 check uP D 64083 I Of i l t er and am pl i f er ci rcui t Y es check TE A 6425D 1 pi ...

Page 43: ...n onl y D V I col our di ssi m i l at i on al l col our di ssi m i l at i on check A D 9883A and 74LV 16244 R Ў ў G Ў ў B di gi t al si gnal check S i l 161B У л and 74LV 16244 R Ў ў G Ў ў B di gi t al si gnal change U 8 24LC 21A Ј checkЈ Ё 5Ј Ј Ё 6Ј pi n norm al changeu7 24LC 21A Ј check Ј Ё 5Ј Ј Ё 6Ј norm al check m ai nboard panel j ack norm al D S 90C 383A norm al check P W 113 out put vi deo ...

Page 44: ...heck P W 1235 out put dat a check V P C 3230 out put check V P C 3230 i nput si gnal check and change P W 1235 N o check and change V P C 3230 pl ane crossband i nt erf erence V G A m ode com m endat ory st at e change U 8Ј checkЈ Ё 5Ј 6 pi n D V I m ode com m endat ory st at e onl y V G A Ў ў D V I not com m endat ory st at e change U 7Ј checkЈ Ё 5Ј 6 pi n checkA D 9883A and peri pheral l y devi ...

Page 45: ...ng ci rcui t C 629Ў ў C 630Ў ў FB 5Ў ў FB 6Ў ў C 522Ў ў C 543 Y es check and change TA 2024 norm al check M S P 3410G i nput si gnal check 67 pi n S I S F i nput TV check sound i nput ot her source check M S P 3410G pow erЎ ў cl ockЎ ў reset Ў ў bus Y es Y es checkTD Q 6F7out p ut S I Fsi gnal check S I F f i l t er am pl i f er ci rcui t norm al check and change TD Q 6F7 abnorm al i t y check and...

Page 46: ...46 Annex 1 Ч Е д Н ј ...

Page 47: ...47 Annex 2 ...

Page 48: ...48 µ з Ф ґ В Л І Ё Жч Ч й ј ю Д Ъ Б Є µ з Ф ґ П Я Ц ч е Ч й ј ю ґ ј ь е Ч й ј ю е Ч й ј ю ...

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