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Table 5.1 PCIE Interface pin definition
miniSAS HD pin
Note
Pin internal processing
RX [15:0]P/N
PCIE input signal
External AC coupling
capacitance
TX [15:0]P/N
PCIE output signal
External AC coupling
capacitance
SMCLK
SMBUS interface clock signal
4.7 KΩ pull-up to 3.3 V
SMDAT
SMBUS interface data signal
4.7 KΩ pull-up to 3.3 V
PERST#
Reset signal
REFCL K P/N
PCIE clock signal
PRESENT
Opposite side in position detection signal
4.7 KΩ pull-up to 3.3 V
5.2 MLU-LINK interface description
MLU-X1001 accelerator is equipped with 4 MLU290-M5 intelligent accelerating cards, each card has
6 MLU-LINK ports. Among them, 4 ports are used for internal interconnection and 2 ports are used for
external interconnection. The MLU-LINK interconnection topology between the internal cards is as
follows:
