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24
GR-CPCIS-XCKU
Document Data Sheet & User Manual
Feb 2022, Version 1.2
1.
A chain with GR716 as the Master, the FPGA, UCD9090 Power Sequencer and FMC board
as Slaves. The Slave addresses of the FPGA and FMC board depend on the logic implemented
in the design
2.
A chain with FPGA as Master (if board is in a Host backplane slot) or as Slave (if the board
is installed in a Peripheral backplane slot). The Slave addresses of the depend on the
corresponding logic implemented.
Figure 12
Board I2C Interfaces
4.6.7
JTAG
Two JTAG Chains are present in the designed:
1.
JTAG1: This JTAG chain allows programming of the FPGA and its attached SPI Prom via a
Digilent HS-2 JTAG module and dedicated front panel USB connector, J2 (marked ‘
FPGA-
JTAG’
on the front panel). The JTAG signals are also available on a 14 pin header J14.
2.
JTAG2: This JTAG chain connects to the JTAG signals of the FMC Mezzanine expansion
connector via a FTDI USB to Serial Converter IC (section 4.6.4) and dedicated front panel
USB connector, J3 (marked ‘
FTDI’
on the front panel).