- Lepton
7
x1 - Lepton
7
x4 - Technical Information Manual
12
Fig. 3.2: BSL sequence
The BSL program execution starts when TST pin has received a minimum of two positive transitions
and if TST is high while /RST rises from low to high. BSL_SEL shall be at high level before BSL starts.
Pulses length and distance between edges of all signals shall be 10ms at least.
Optional connections:
•
GPIOs allow interaction with the R7101C Lepton
7
x1/R7104C Lepton
7
x4 as both digital inputs and
outputs. They may be used to trigger inventory, generate events based on inventory activity, or
provide general-purpose user-controlled digital I/O.
•
WKUP provides a mechanism to wake up the R7101C Lepton
7
x1/R7104C Lepton
7
x4 from the low
power Sleep mode. If unused, this pin should be tied to logic low.
Power Supply
The R7101C Lepton
7
x1/R7104C Lepton
7
x4 is powered by a voltage applied to the VDC_IN pin (pin 3 and 4)
relative to the GND pins. The supply voltage operating range is 3.2V to 5.25V. Power consumption varies
from about 8W to about 80mW depending on the operating mode. The power supply is internally bypassed
and regulated, and no external bypass or bulk storage capacitance is required, as long as the input voltage
is stable.
If R7101C Lepton
7
x1/R7104C Lepton
7
x4 activity is not required at all times, and power reduction is desired,
the VDC_IN supply voltage may be externally gated to remove power to the device.
RF Connection
The Lepton
7
x1 R7101C has a single MMCX jack RF port, the Lepton
7
x4 R7104C has four MMCX jacks RF
ports. Each RF port shall be connected t
o a 50 Ω antenna via
a MMCX plug and
50 Ω
cable.
UART Communication
The R7101C Lepton
7
x1/R7104C Lepton
7
x4 has one full-duplex UART standard interface, accessible using
pins UART-RX, UART-TX. Such UART implements the host communication interface via easy2read
©
. The Tx
pin is output from the R7101C Lepton
7
x1/R7104C Lepton
7
x4, the Rx pin is input to the R7101C
Lepton
7
x1/R7104C Lepton
7
x4. Interface settings are by default 921,600 baud, with 8 data bits, 1 stop bit,
and no parity bit (8-n-1 configuration).
UART interface signals are 3.3 V relative to GND. The specific VIH, VIL, VOH and VOL specifications may be
found in the §
Device Input and Output Specifications
paragraph page 17. The TX pin is driven strong high
and low with a sink/source current of about 8 mA. If the load on a pin draws more than the 8 mA sink and
source current, the pin is not guaranteed to meet the VOH and VOL specs listed in §
paragraph page 17. Excessive current sunk or sourced on the GPIO pins can also cause
electrical damage to the device.
Warning
: Voltages outside of the maximum IO operating voltage range of -0.3 to 4.0 V should
not be applied to the UART pins. This can cause permanent damage to the device.
