Cactus Technologies, Limited
Bit 6
This bit is an X (Do not care).
Bit 5
This bit is an X (Do not care).
Bit 4
This bit is an X (Do not care).
Bit 3
This bit is ignored by the drive.
Bit 2 (SW Rst)
This bit is set to 1 in order to force the drive to perform an AT Disk controller Soft
Reset operation. The drive remains in Reset until this bit is reset to '0'.
Bit 1 (-IEn)
The Interrupt Enable bit enables interrupts when the bit is 0. When the bit is 1,
interrupts from the drive are disabled. This bit is set to 0 at power on and Reset.
Bit 0
This bit is ignored by the drive.
4.1.11. Drive Address Register
This register is provided for compatibility with the AT disk drive interface. It is recommended
that this register not be mapped into the host's I/O space because of potential conflicts on
Bit 7. The bits are defined as follows:
D7
D6
D5
D4
D3
D2
D1
D0
X
-WTG
-HS3
-HS2
-HS1
-HS0
-nDS1
-nDS0
Bit 7
This bit is unknown.
Implementation Note:
Conflicts may occur on the host data bus when this bit is provided by a Floppy Disk Controller
operating at the same addresses as the SSD. Following are some possible solutions to
this problem:
1. Locate the SSD at a non-conflicting address (i.e., Secondary address (377) when a Floppy
Disk Controller is located at the Primary addresses).
2. Do not install a Floppy and a SSD in the system at the same time.
3. Implement a socket adapter that can be programmed to (conditionally) tri-state D7 of I/0
address 3F7/377 when a SSD product is installed and conversely to tri-state D6-D0 of
I/O address 3F7/377 when a floppy controller is installed.
4. Do not use the SSD’s Drive Address register. This may be accomplished by either a) If
possible, program the host adapter to enable only I/O addresses 1F0-1F7, 3F6 (or 170-
177, 176) to the SSD or b) if provided use an additional Primary/Secondary
configuration in the SSD that does not respond to accesses to I/O locations 3F7 and
377. With either of these implementations, the host software must not attempt to use
information in the Drive Address Register.
Bit 6 (-WTG)
This bit is 0 when a write operation is in progress, otherwise, it is 1.
Bit 5 (-HS3)
This bit is the negation of bit 3 in the Drive/Head register.
Bit 4 (-HS2)
This bit is the negation of bit 2 in the Drive/Head register.
Bit 3 (-HS1)
This bit is the negation of bit 1 in the Drive/Head register.
Bit 2 (-HS0)
This bit is the negation of bit 0 in the Drive/Head register.
Bit 1 (-nDS1)
This bit is 0 when drive 1 is active and selected.
Bit 0 (-nDS0)
This bit is 0 when the drive 0 is active and selected.
5.ATA Command Description
This section defines the ATA command set supported by the Cactus Technologies
®
CFast
card.
Cactus Technologies Limited
Industrial Grade CFast Card Product Manual
v1.1
16
