Broadcom BCM5220 Application Note Download | Manualshive

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BCM5221

Product Application Note

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BCM5220

7/7/00

Bro a d c o m C o rp o r a t i o n

Page 15

5221/5220-AN01 Product Application Note, Revision R

Figure 8:

Multiport Power Plane Example

10/100 T

WISTED

P

AIR

MII

TO

MDI

Figure 9 on page 16 represents a typical 10/100 twisted pair DTE implementations, MII to MDI inclusive, for the BCM5221.
This example assumes the use of 2.5V VDD for the system, with the digital interface running at 3.3V.

Logic Power Plane (2.5V or 3.3V)

Ma

gn

et

ic

s

M

a

gne

ti

c

s

BCM5221

RJ45-8

RJ45-8

ASIC /

MAC

ASIC /

MAC

BCM5221

Chassis Ground Plane

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Summary of Contents for BCM5220

Page 1: ...16215 Alton Parkway P O Box 57013 Irvine CA 92619 7013 Phone 949 450 8700 Fax 949 450 8710 APPLICATION NOTE BCM5221 5220 7 7 00 ...

Page 2: ...Broadcom Corporation All rights reserved Printed in the U S A Broadcom the pulse logo and QAMLink are registered trademarks of Broadcom Corporation and or its subsidiaries in the United States and certain other countries All other trademarks are the property of their respective owners ...

Page 3: ...Broadcom Corporation Document 5221 5220 AN01 R Page iii Application Note BCM5221 7 7 00 BCM5220 REVISION HISTORY REVISION DATE CHANGE DESCRIPTION AN01 R 7 7 00 Initial release ...

Page 4: ... 4 PHYAD4 CK25 5 PHYAD3 PAUSE 5 PHYAD2 ACT_LED 5 PHYAD1 COL_LED 5 PHYAD0 FDX_LED 5 SPDLED ADV_PAUSE 5 100Base FX 5 SD 7 RD 7 TD 7 Serial 10m 7 Wire Interface 7 Auto MDI MDIX Crossover 8 Magnetics 9 Bel 9 Pulse Engineering 9 Halo 9 Media Conversion 10 Cable Length Monitoring Capability 12 JTAG Considerations 12 JTAG Functional Description 13 Eliminating Tri State Buffer Requirement 13 Preferred Met...

Page 5: ...sted Pair MII to MDI 15 General Layout Notes 17 Analog Related Passive Component Placement 17 TD Trace Routing 17 100Base TX and 10Base T Signaling 17 RD Trace Routing 17 Reference Clock 17 Magnetics to RJ45 8 17 Chassis Ground 17 Board Layer Allocation 18 Power Supply Filter Component Placement 19 General Layout Recommendations 20 Thermal Information 21 BCM5221 vs BCM5220 21 ...

Page 6: ... BCM5221 data sheet and other 5221 application notes in order to ensure the most robust design possible The BCM5221 is available in a 64 pin 10 mm2 PQFP package part number BCM5221KPT The BCM5221 is also available in a 64 ball 8 mm2 FBGA package part number BCM5221KPB This is the lowest power highest performing single channel PHY available today The BCM5220 is identical to the BCM5221 with the exc...

Page 7: ...and pull down is approximately 50 kΩ 20 REF_CLK pull down TXD 3 0 pull down TXEN pull down TXER pull down MDC pull down PHYAD 4 0 pull down FDX pull down SD pull down SD pull down OVDD DVDD REGDVDD AVDD AVDD BIASVDD REGAVDD DVDD 2 5V 2 5V N C N C 2 5V BCM5221 2 5V Supply Connection OVDD DVDD REGDVDD AVDD AVDD BIASVDD REGAVDD DVDD N C 3 3V BCM5221 3 3V Supply Connection N C BIASVDD connects to AVDD...

Page 8: ...pacitance of 18 pF A calculation for deriving the approx imate load capacitance is CL1 x CL2 CL1 CL2 Cs Where CL1 x CL2 are the actual load capacitors connected to either side of the crystal and Cs is the sum of the stray capacitance and input pin capacitance of the PHY device Assuming load caps of 20pF each and a total stray parasitic capacitance of approximately 8pF the above equation yields a t...

Page 9: ...own Mode Manual Low Power mode LOW_PWR pin 1 configures the device such that all circuitry with the exception of the Energy Detect block is powered down This mode results in maximum device current consumption of approximately 10mA This Energy Detect circuit asserts the ENERGY_DET output when receive energy is detected at the RD wire side inputs Spe cifically if energy of at least 300 mV pk pk diff...

Page 10: ...put that along with the other 4 PHYAD pins sets a unique address for this de vice to allow MDIO access The COL_LED output is an active low indication of collision and only meaningful during half duplex operation logic 0 collision logic 1 no collision If the use of this LED output is required Broadcom recommends that PHYAD1 be strapped high because the LED output polarity is active low PHYAD0 FDX_L...

Page 11: ... a controlled impedance trace Placement of the dividing networks is noncritical 3 3V BRCM5221 Fiber Transceiver Receive Termination RD RD RD RD 130Ω 1 16W 1 130Ω 1 16W 1 Route each signal trace with a controlled impedance of 50Ω if the r o u t i n g d i s t a n c e exceeds one inch 12Ω 1 16W 1 12Ω 1 16W 1 68Ω 1 10W 1 68Ω 1 10W 1 3 3V Place this termination network close to the BCM5228 input BRCM52...

Page 12: ...to either the BCM5221 or the fiber optic transceiver is non critical As with any interface trace lengths should be kept to a minimum wherever possible The SD input of the BCM5221 requires an external bias of 1 7V to ensure that the differential SD input functions properly RD Because the RD inputs of the BCM5221 are internally biased and because typical 3 3V fiber transceivers nor mally source PECL...

Page 13: ...RD When connected via a straight through cable to another device that does not perform the Auto MDI MDIX crossover the BCM5221 automatically switches its transmitter to RD and its receiver to TD to communicate with the remote device If two devices are connected that both have Auto MDI MDIX crossover capability then a random algorithm determines which end performs the crossover function The Auto MD...

Page 14: ...IX operates only on the transmit and receive data pairs swapping them if required It does not operate on the individual wires within a given pair and therefore cannot correct for possible polarity swap issues However the 10BASE T transceiver within the BCM5221 includes polarity detection and correction to ensure proper functionality should a polarity problem exist in the wiring Note that 100Base T...

Page 15: ...eclude the use of a BCM5221 media converter in a half duplex system The following pin strapping is required for Media Conversion Pull up and pull down values of 4 7 KΩ are recommended 100BASE TX PHY LINKLED MEDIA_CONV pin 35 must be pulled low MII_EN pin 18 must be pulled low ANEN pin 38 must be pulled low F100 pin 37 must be pulled high or left unconnected FDX pin 39 must be pulled high SD and SD...

Page 16: ... 1nF 0 01uF 3 6 2 1 RXD1 RXD0 TXD1 TXD0 TXEN CRS_DV REF_CLK REF_CLK BCM5221 PHY 100BASE FX RXD0 RXD1 TXD0 TXD1 TXEN CRS_DV 50MHz 50ppm Xtal based clock source Clock source must not be PLL based 50MHz SD SD TD TD RD RD SD Fiber Transceiver 100BASE FX Mini MTRJ TD TD RD RD Voltage Divider 1 7V Refer to 100BASE FX section in this application note for termination details Series Source Termination requ...

Page 17: ...ng should be carefully considered if the use of JTAG is required This pin sharing approach provides JTAG functionality within the feature rich BCM5221 JTAG test mode is only enabled when the active high JTAG_EN input is pulled high When JTAG_EN is enabled the follow ing pins become the JTAG test interface for the BCM5221 Table 1 Cable Length Estimate Register 1Bh 14 13 12 Cable Length in Meters 00...

Page 18: ... output signals during normal operation ELIMINATING TRI STATE BUFFER REQUIREMENT Preferred Method If the design does not require LNKLED and SPD_LED signals it is possible to connect the JTAG TDI and TMS signals directly to the TDI and TMS pins of the BCM5221 Eliminating the TDI tri state buffers is accomplished by the following two writes 1 Enable shadow register by writing a 1to bit 7 of MII regi...

Page 19: ...efined below See Figure 1 on page 2 OVDD This pin supplies power to the digital input and output buffer stages of the BCM5221 By connecting OVDD to a 3 3V power rail all of the 3 3V tolerant digital inputs accepts either CMOS or TTL input signaling or static levels If the system design allows for all input signaling to be limited to a maximum swing of 2 5V the OVDD pin can be connected to the 2 5V...

Page 20: ... 10 100 TWISTED PAIR MII TO MDI Figure 9 on page 16 represents a typical 10 100 twisted pair DTE implementations MII to MDI inclusive for the BCM5221 This example assumes the use of 2 5V VDD for the system with the digital interface running at 3 3V Logic Power Plane 2 5V or 3 3V Magnetics Magnetics BCM5221 RJ45 8 RJ45 8 ASIC MAC ASIC MAC BCM5221 Chassis Ground Plane ...

Page 21: ... 5 1000pF Cer 5 This configuration selects a PHY Address of 00000 TESTEN and LOWPWR are internally pulled low the XMTLED INTR FDXLED LED output is Open Drain Because TXC and RXC run at 25MHz during 100BASE X mode source termination resistors are recommended in order to help control potential reflections 49 9Ω 1 16W 1 49 9Ω 1 16W 1 1000pF Cer 5 1 27KΩ 1 16W 1 49 9Ω 1 16W 1 49 9Ω 1 16W 1 VDD 2 5V 10...

Page 22: ...ptimal integrity it is recommended that the controlled impedance transmit path from the PHY to the magnetics be kept as short and direct as possible with minimum vias and with properly placed termination RD Trace Routing The RD and RD traces which connect the receive transformer to the PHY should be routed with a differential characteristic impedance of 100Ω and should be routed adjacent to a grou...

Page 23: ...tion Note Revision R Page 18 Board Layer Allocation Figure 10 on page 19 illustrates one option for board layer allocation The figure gives an ex ample based on a single VDD and single Ground plane Of course some applications will require a second VDD plane in order to accommodate a second power rail ...

Page 24: ...e these general placement guidelines to ensure optimal performance Power Plane Mag RJ45 8 ASIC MAC Layer 1 top component signal and Chassis Gnd Layer 3 Power signal Layer 4 bottom signal chassis GND components optional Layer 2 Ground signal Mag RJ45 8 ASIC MAC BCM5221 signal routing Chassis Ground Mag RJ45 8 ASIC MAC BCM5221 Ground plane signal routing BCM5221 Chassis Ground Mag RJ45 8 ASIC MAC BC...

Page 25: ...er even though it would have to be on separate layers always cross them at 90 degrees to minimize potential crosstalk Always place power supply filter components as close as possible to the recommended pins see Figure 8 on page 15 in order to maximize the filtering effects If a filter component cannot be directly connected to a given power pin with a very short and fat etch do not connect it via c...

Page 26: ...al information pertaining to the BCM522KPB and BCM5221KPT package types Table 3 and Table 4 provide a comparison of Theta JA versus Airflow Theta JC for this package is given as 21 23 C W Additionally the BCM5221KPB is designed for and rated for a maximum Junction Temperature of 125C Theta JC for this package is given as TBD Additionally the BCM5221KPT is designed for and rated for a maximum Junct...

Page 27: ...ty function or design Information furnished by Broadcom Corporation is believed to be accurate and reliable However Broadcom Corporation does not assume any liability arising out of the application or use of this information nor the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others BCM5221 Product Appli...

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