BL602/604 Reference Manual
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
RFIU
RFIO
TFIU
TFIO
RFI
CLR
TFI
CLR
UDR
EN
UDT
EN
Bits
Name
Type
Reset
Description
31:8
RSVD
7
RFIU
R
1’b0
Underflow flag of RX FIFO, can be cleared by rx_fifo_clr
6
RFIO
R
1’b0
Overflow flag of RX FIFO, can be cleared by rx_fifo_clr
5
TFIU
R
1’b0
Underflow flag of TX FIFO, can be cleared by tx_fifo_clr
4
TFIO
R
1’b0
Overflow flag of TX FIFO, can be cleared by tx_fifo_clr
3
RFICLR
W1C
1’b0
Clear signal of RX FIFO
2
TFICLR
W1C
1’b0
Clear signal of TX FIFO
1
UDREN
R/W
1’b0
Enable signal of dma_rx_req/ack interface
0
UDTEN
R/W
1’b0
Enable signal of dma_tx_req/ack interface
10.4.15 uart_fifo_config_1
Address
:
0x4000a084
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
RFITH
RSVD
TFITH
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
RFICNT
RSVD
TFICNT
Bits
Name
Type
Reset
Description
31:29
RSVD
28:24
RFITH
R/W
5’d0
RX FIFO threshold, dma_rx_req will not be asserted if tx_-
fifo_cnt is less than this value
23:21
RSVD
20:16
TFITH
R/W
5’d0
TX FIFO threshold, dma_tx_req will not be asserted if tx_-
fifo_cnt is less than this value
15:14
RSVD
13:8
RFICNT
R
6’d0
RX FIFO available count
7:6
RSVD
BL602/604 Reference Manual
140/ 195
@2020 Bouffalo Lab