BL602/604 Reference Manual
when idle, CPOL = 0 means the idle level is low, and CPOL = 1 means the idle level is high. CPHA is used to determine
the sampling time. CPHA = 0 samples on the first clock edge of each cycle, and CPHA = 1 samples on the second
clock edge of each cycle.
By setting registers SPI_PRD_0 and SPI_PRD_1, you can also adjust the start and end level duration of the clock,
the time of phase 0/1, and the interval between each frame of data. The specific settings in the four modes are shown
below:
SPICLK
Signal Options:
Clock Polarity = 0
Clock Phase = 0
Clock Polarity = 1
Clock Phase = 1
Clock Polarity = 1
Clock Phase = 0
Clock Polarity = 0
Clock Phase = 1
SPISCS[n]
%
.
Figure 9.1: SPI clock
The meaning of each number is as follows: 1 is the length of the start condition, 2 is the length of the stop condition,
3 is the length of phase 0, 4 is the length of phase 1, and 5 is the interval between each frame of data.
9.3.2 Master continuous transmission mode
When this mode is enabled, the CS signal will not be released when the current data is transmitted and there is still
data available in the FIFO.
9.3.3 Acceptance filtering function
By setting the start and end bits that need to be filtered out, the SPI discards the corresponding data segment in the
received data. As shown below:
BL602/604 Reference Manual
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