bonitron M3452, Customer Reference Manual

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M3452 vR7 EIP/PDP
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The dynamic master switching sequence should follow these steps:
•
Disable all modules by opening the “Enable” input. Bus
regulation stops.
•
Close “Master Select” contact on a single module.
•
Ensure that only one Master/Slave Status contact is closed in
the system, indicating that only one module is master.
•
Enable all modules. Bus regulation resumes.
4.2.4.
F
IELDBUS
I/O
4.2.4.1.
M
EMORY
M
AP
The R7EIP and R7PDP modules have an embedded digital network
module. This module is an Acromag 983EN-2012 or 983DP-2012. The
configuration files and manuals for these modules are available on either
the Bonitron website or the Acromag website.
The memory map shows the position of the control and status bits in
relation to the base address on the network. Detailed descriptions of each
bit and register are in the previous sections.
The memory map is word based, each word using 16 bits.
This module has bidirectional connections for inputs and outputs. Care
must be taken when programming, as input bits will override the output
bits if set in the wrong addresses.
Figure 4-1: M3452R7 Memory Map