19
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ENET_TX_CTL
Ethernet MAC Transmit enable control
64
ENET_TX_CTL
ENET_MDC
MAC and PHY Communication clock
80
ENET_MDC
ENET_MDIO
MAC and PHY Communication data
82
ENET_MDIO
ENET_nINT
ENET interrupt
186
GPIO1_IO10
2.5 USB
Two USB controllers and PHYs that support USB 2.0 and OTG. Each USB instance contains USB 2.0
core, which can operate in 2.0 mode.
Signal
Description
Pin
Defaults Function
USB1_DP
USB1 positive data
85
USB1_DP
USB1_DN
USB1 negative data
87
USB1_DN
USB1_ID
USB1 OTG ID signal
140 USB1_ID
USB1_VBUS_DET
USB1 VBUS detect
136 USB1_VBUS_DET
USB2_DP
USB2 positive data
79
USB2_DP
USB2_DN
USB2 negative data
81
USB2_DN
USB2_ID
USB2 OTG ID signal
138 USB2_ID
USB2_VBUS_DET
USB1 VBUS detect
134 USB2_VBUS_DET
2.6 PCIe
PCI-E Features:
•
Single lane supporting PCIe Gen2
•
Dual mode operation to function as root complex or endpoint
•
Integrated PHY interface
•
Support L1 low power sub-state
Signal
Description
Pin
Defaults Function
PCIE_RXP
PCIE receive data positive
103 PCIE_RXP
PCIE_RXN
PCIE receive data negative
105 PCIE_RXN
PCIE_TXP
PCIE transmit data positive
97
PCIE_TXP
PCIE_TXN
PCIE transmit data positive
99
PCIE_TXN
PCIE_CLKP
PCIe reference clock dif input positive
91
PCIE_CLKP
PCIE_CLKN
PCIe reference clock dif input negative
93
PCIE_CLKN
2.7 EMMC/SD/SDIO
2.7.1 EMMC 5.1
⚫
Fully compliant with MMC v5.1/v5.0/v4.4/v4.41/v4.4/v4.3/v4.2
⚫
Support 1bit,4bit(ddr), 8bit(ddr) mode,
⚫
Up to HS400 speed mode