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Preliminary

Trigger

The Karbon

KBN-7-2

BitFlow, Inc.

Version F.0

7.2 Trigger

7.2.1 Trigger Input Types

There are four trigger inputs.

TRIGGER_TTL - Single ended TTL level trigger
TRIGGER_DIFF - Differential (LVDS) trigger
TRIGGER_OPTO - Optocoupled trigger
FEN - The FEN signal on the CL1 connector.

The hardware trigger is enabled/disabled by the bit EN_TRIGGER. Only one input at a
time is active (the software trigger bit, SW_TRIG, is always active). The active trigger is
selected by the bitfield SEL_TRIG. The current level of these inputs can be read from
software by reading the bits RD_TRIG_DIFF, RD_TRIG_TTL, RD_TRIG_OPTO and RD_
FEN. The unselected triggers will have no effect on the board. However, they can be
used as general purpose inputs.

7.2.2 The Optocoupled Trigger

The opto-coupled trigger allows the acquisition circuitry to accept a trigger signal
without having a galvanic connection to the trigger source. This is mandatory in some
medical and industrial application. The trigger information is passed as a light pulse
from an on-board LED that is coupled to a receiving phototransistor. The LED and the
phototransistor are in the same package, a Sharp PC3H711. Figure 7-1 shows the
electrical diagram of the optocoupled trigger circuit and a suggested circuit for the
driver. The LED is driven by an open collector driver. The user must supply his +5V
power to the LED. Note that there is no galvanic connection between the user’s circuit
and the acquisition circuitry.

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Summary of Contents for KBN-CL4-2.51-SP

Page 1: ... r e l i m i n a r y The Karbon CL Hardware Reference Manual BitFlow Inc 300 Wildwood Ave Woburn MA 01801 USA Tel 781 932 2900 Fax 781 933 9965 Email support bitflow com Web www bitflow com Revision F 0 ...

Page 2: ...tFlow Inc BitFlow Inc makes no implicit warranty for the use of its products and assumes no responsibility for any errors that may appear in this document nor does it make a commit ment to update the information contained herein BitFlow Inc retains the right to make changes to these specifications at any time without notice All trademarks are properties of their respective holders Revision History...

Page 3: ...n CL Models KBN 1 11 2 Acquisition and Camera Control Introduction KBN 2 1 BitFlow s Flow Thru Architecture KBN 2 2 Camera Specific Firmware KBN 2 5 Generation of Acquisition Windows KBN 2 7 The Horizontal Active Window HAW KBN 2 7 The Vertical Active Window VAW KBN 2 8 The Control Tables CTABs KBN 2 10 Vertical Control Table KBN 2 10 The VCTAB Functions KBN 2 11 Horizontal Control Table KBN 2 13 ...

Page 4: ...ter KBN 4 15 CON3 Register KBN 4 21 CON4 Register KBN 4 24 CON5 Register KBN 4 31 CON6 Register KBN 4 37 CON7 Register KBN 4 39 CON8 Register KBN 4 41 CON9 Register KBN 4 46 CON10 Register KBN 4 50 CON11 Register KBN 4 54 CON12 Register KBN 4 56 CON13 Register KBN 4 58 CON14 Register KBN 4 60 CON17 Register KBN 4 64 CON18 Register KBN 4 66 CON19 Register KBN 4 68 CON20 Register KBN 4 70 CON21 Regi...

Page 5: ...formation KBN 6 6 Scatter Gather DMA Instructions KBN 6 7 Destination Address KBN 6 8 Size of Transfer KBN 6 9 Next Quad Address KBN 6 10 7 Electrical Interfacing Introduction KBN 7 1 Trigger KBN 7 2 Trigger Input Types KBN 7 2 The Optocoupled Trigger KBN 7 2 Encoder KBN 7 4 Encoder Input Types KBN 7 4 The Optocoupled Encoder KBN 7 4 General Purpose Inputs GPIN KBN 7 6 General Purpose Outputs GPOU...

Page 6: ...BN 9 1 The Karbon CL Connectors KBN 9 3 The CL Connectors KBN 9 3 The I O Connector KBN 9 4 The Auxiliary Connectors KBN 9 4 The Jumpers and Switches KBN 9 5 Jumpers KBN 9 5 Switches KBN 9 7 The Camera Link Connector Pinouts CL1 to CL4 KBN 9 8 The I O Connector Pinout P11 KBN 9 9 ...

Page 7: ...port Our web site is www bitflow com Technical support is available at 781 932 2900 from 9 00 AM to 6 00 PM Eastern Stan dard Time Monday through Friday For technical support by email support bitflow com or by FAX 781 933 9965 please include the following Product name Camera type and mode being used Software revision number Computer CPU type PCI chipset bus speed Operating system Example code if a...

Page 8: ...ions that are used for numerical notation in this manual Table P 2 shows the numerical abbreviations that are used in this manual Table P 1 Base Abbreviations Base Designator Example Binary b 1010b Decimal None 4223 Hexidecimal h 12fah Table P 2 Numeric Abbreviations Abbreviation Value Example K 1024 256K M 1048576 1M ...

Page 9: ...s Note that we are not using the word virtual here in the sense of a software virtualiza tion of a hardware device these VFGs are real hardware The reason we using vir tual is because the term frame grabber has more than one meaning It can mean the piece of hardware that you put in your computer or it can mean the device that the your software application is controlling and getting images from For...

Page 10: ...d opens the door to unlimited customization To understand which models support which modes see Section 1 4 Also to see exam ples of the different modes see Section 1 3 However keep in mind the Karbon is only limited by your imagination if you need a mode you don t see just let us know 1 1 3 Karbon Configuration Spaces The four basic Karbon CL boards support from one to four VFGs Each VFG has its o...

Page 11: ...tFlow Inc KBN 1 3 Figure 1 1 KBN PCE CL2 D and KBN PCE CL4 D KBN PCE CL4 D only CL Connector 2 Channel Link Chip PCI Device 0 PCI Device 1 PCI Device 2 PCI Device 3 Channel Link Chip Channel Link Chip Channel Link Chip PCI Express Bus CL2 CL Connector 3 CL3 CL Connector 4 CL4 CL Connector 1 CL1 ...

Page 12: ... Inc Version F 0 Figure 1 2 KBN PCE CL2 F and KBN PCE CL4 F KBN PCE CL4 F only CL Connector 2 Channel Link Chip PCI Device 0 PCI Device 1 Channel Link Chips Channel Link Chip Channel Link Chips PCI Express Bus CL2 CL Connector 3 CL3 CL Connector 4 CL4 CL Connector 1 CL1 ...

Page 13: ...era then the slave VFG will also have to be configure for a two tap odd even pixel camera In all other ways however the two configurations do not have to match If you have a requirement where this rule must be broken please contact BitFlow s support department Custom combinations of firmware are available If there is a mismatch between the firmware required by one VFG s camera file and the firmwar...

Page 14: ... of configurations The block diagrams of the cur rent supported configurations is shown in Figure 1 3 Subequent sections discussed the details of the various models Figure 1 3 Karbon CL Hardware Platform As discussed previously the Karbon platform can support a number of different vir tual frame grabber arrangements Thus the hardware resources seen in Figure 1 3 can be utilized in a number of diff...

Page 15: ...me grabber VFG that is support on the Kar bon CL hardware Since the Full CL interface requires two CL connectors the KBN PCE CL2 F can only support one of these virtual frame grabbers and the KBN PCE CL4 F can support two of these virtual frame grabbers Figure 1 4 Full CL Virtual Frame Grabber The Full CL VFG implements the Camera Link full configuration i e it can accept a sin gle camera putting ...

Page 16: ... The PCI interface block handles host reads writes to from the board These reads writes are used to program the board and to control its modes This block is also responsible for DMAing image data to the host memory or other devices The DMA engine uses chaining scatter gather DMA which can DMA a virtually unlimited amount of data to memory without using any CPU cycles There is an on board UART as r...

Page 17: ... block has the Channel Link IC the Camera Control drivers and the serial communication tran ceivers The MUX block packs and assembles the data from the Camera Link block before it is pushed into the FIFO This block re arranges on the fly the data from the camera s taps so that the data is written in raster scan format in the host memory The FIFO block Kilobytes deep decouples the camera from the D...

Page 18: ...lock handles host reads writes to from the board These reads writes are used to program the board and to control its modes This block is also responsible for DMAing image data to the host memory or other devices The DMA engine uses chaining scatter gather DMA which can DMA a virtually unlimited amount of data to memory without using any CPU cycles There is an on board UART as required by the CL sp...

Page 19: ...of the cameras that you connect to the same Karbon There are also no restrictions on the synchronization between the cameras Not only do they no need to be syncrhonized they don t even need to be acquiring at the same time As far as your application is concerned each camera con nected to the Karbon CL has it s own independent frame grabber Table 1 1 Karbon CL Models Capability KBN PCE CL2 D KBN PC...

Page 20: ...P r e l i m i n a r y The Karbon CL Models The Karbon KBN 1 12 BitFlow Inc Version F 0 ...

Page 21: ...cquisition and Camera Control Introduction Version F 0 BitFlow Inc KBN 2 1 Acquisition and Camera Control Chapter 2 2 1 Introduction This section covers acquisition and camera control for the R64 CL Karbon CL and the Neon CL ...

Page 22: ... clocks This is useful for accurate alignment of the video on the display The Video Selector selects the data source the video from the camera or the on board generated synthetic video The various patterns of synthetic video are useful mainly for the on board Built In Self Test BIST The Mask is a 32 bit mask replicated over the upper and lower 32 bits of the 64 bit data path The purpose of this ma...

Page 23: ... Inc KBN 2 3 The amount of data written in the FIFOs is controlled by the Acquisition Window The vertical and horizontal size of this window is programmed in the ALPF and the ACLP registers respectively see Section 2 4 The timing of this window is determined by the camera and the acquisition state machine ...

Page 24: ...hip Y Channel X Equalizer FIFO Channel Y Equalizer FIFO Channel Z Equalizer FIFO Camera Link Pixel Data Descrambler Synthetic Video VID_SOURCE PIX_DEPTH VIDEO_MASK CLIP FORMAT DISPLAY PIX_DEPTH SHIFT_RAW SHIFT_DSP SHIFT_RAW_LEFT SHIFT_DISP_LEFT SHIFT_DISP_SELECT Barrel Shifter Barrel Shifter Barrel Shifter Barrel Shifter 2 1 MUX 32 Bit Mask 32 Bit Mask Raster Scan Line Reformatter 8 Bit Clip 8 Bit...

Page 25: ...formats is shown in Table 2 1 Table 2 1 Firmware Options FORMAT Firmware Name Format Description 0 MUX 1 tap cameras 1 MUX_2TOEP 2 taps odd even pixels 2 MUX_2TOEL 2 taps odd even lines 3 MUX_2TS 2 taps segmented 4 MUX_2TS1RI 2 taps segmented right inverted 5 MUX_4TS 4 taps segmented 6 MUX_4T2S2RIOEP 4 taps odd even pixels right taps inverted 7 MUX_4TQ2RI2BU 4 quads right quads inverted bottom qua...

Page 26: ...BitFlow Inc Version F 0 18 MUX_2TOEPI 2 taps odd even pixels both inverted 19 MUX_1TI 1 tap inverted 20 MUX_8WI 8 taps 8 way interleaved 21 MUX_BAY_2TS_RI Bayer decoder 2 taps segmented right inverted Table 2 1 Firmware Options FORMAT Firmware Name Format Description ...

Page 27: ...s Note that the ACPL is not a function of the bits per pixel The relationship between the number of pixels per line and the number of clocks per line is controlled by the firmware currently downloaded to the board The FORMAT register will indi cate which firmware is currently downloaded Each tap configuration requires a differ ent firmware file be downloaded The correct firmware is automatically d...

Page 28: ...he ALPF field is pro grammed in CON17 The 17 bits define the maximum VAW as minimum 128K lines The total number of lines per frame that will be acquired can be different than the ALPF For a dual tap camera that supplies odd even lines for example the total num ber of lines acquired will be twice the ALPF as in the period of one HAW the camera supplies two lines The size of the VAW is on an arbitra...

Page 29: ... y Acquisition and Camera Control Generation of Acquisition Windows Version F 0 BitFlow Inc KBN 2 9 Figure 2 3 Generation of the Vertical Active Window VAW Vertical CTAB 2 1 MUX VAW Generator ALPF FEN VAW_START VSTART VAW ...

Page 30: ...going to the camera In this case the CTABs can be thought of as pro grammable waveform generators Another bit might cause an interrupt to occur on the PCI bus yet another bit might force the HCOUNT to go to zero The CTABs are fully programmable by software The details of the CTABs are describe in this section 2 5 1 Vertical Control Table Figure 2 4 depicts the structure of the Vertical Control Tab...

Page 31: ...cally scan all the VCTAB s addresses Any arbitrary cyclic waveform can be implemented by programming the VCTAB with the adequate data The LOAD_V and RESET_V will enable the synchronization between external events and the waveforms generated by the VCTAB LOAD_V and RESET_V will force the VCOUNT to known values 8000h and 0 respectively The INC_V signal will allow for stopping the counter from increm...

Page 32: ...UNT is reset there are programmable options defined by VCNT_RLS_ZERO Depending on this bitfield VCOUNT can continue to count or wait at zero till some event occurs usually the assertion of the TRIGGER This operating mode is especially useful for synchronizing cameras to external events TRIGGER is usually the output of a part in place signal Until this signal is asserted the VCOUNT waits at address...

Page 33: ...arks the start of a valid frame The start of the ver tical acquisition window can be placed starting at address 8000h ENVLOAD is a column in the VCTAB There are cameras that do not assert FEN Some other type of cameras assert only the start and stop of a frame In this case ENVLOAD can mask out the unwanted signals Operation on the rising falling edge of FEN is selected by FENPOL see CON14 The RESE...

Page 34: ...ed with the value of 2000h Logic for generating RESET_H the reset control signal to the HCOUNT When RESET_H is asserted HCOUNT is reset to 0 HCTAB a static memory SRAM that outputs eight HCTAB control signals The address of this SRAM is driven by HCOUNT Logic for generating CLOCK_H the clock to the HCOUNT This is a frequency divider CLOCK_H is PCLK the pixel clock divided by eight Note If RESET_H ...

Page 35: ...ired only while the HAW is active HRESET will reset the HCOUNT ENHLOAD will allow the loading of the HCOUNT A location that has 1 will allow the loading of the HCOUNT A 0 will inhibit the loading of the HCOUNT GPH are general purpose horizontal functions See usage below The INC_H Control INC_H is the logic for incrementing HCOUNT There are only two instances when we want to inhibit the incrementin...

Page 36: ... HCOUNT will wait at address 00o0h until ENCODER is asserted Horizontal Stick Using the previous example assume that after we asserted the sync signal to the cam era we expect the camera to give us a line i e assert LEN While we expect the cam era to assert LEN HCOUNT is still being incremented If it takes too long for the camera to respond HCOUNT will eventually reach and pass beyond 2000h A hori...

Page 37: ...ons The CT s are four functions derived from the HCTAB and the VCTAB Those functions can define an arbitrary horizontal and or vertical waveform The definition of the CT s is given below CT 0 GPV 0 AND GPH 0 CT 1 GPV 1 AND GPH 1 CT 2 GPV 2 AND GPH 2 CT 3 GPV 3 AND GPH 3 Each CT has a vertical and a horizontal component Both components are pro grammed in the CTABs The minimum horizontal pulse is 8 ...

Page 38: ...ht be to begin acquiring pixels another might be to reset the VCOUNT back to zero Generally these state changes are caused by one or more events There are a number of events both horizontal and vertical that the board can react to These events are tied to operations by a set of programmable bitfields The details of these events are outlined in this section 2 6 1 Vertical Operations and Events The ...

Page 39: ...t not make sense VCOUNT Release From Zero This operation controls the behavior of VCOUNT when it reached zero See Table 2 7 Table 2 6 Vertical Events Event description Event Name TRIGGER asserted TRIG_ASRT TRIGGER de asserted TRIG_DASRT FEN asserted FEN_ASRT FEN de asserted FEN_DASRT TRIGGER is HI TRIG_HI TRIGGER is LO TRIG_LO RESET from VCTAB RST_VCTAB RESET from SW RST_SW Host writes acquisition...

Page 40: ...e stick point The pur pose of the stick point is to allow for very long periods of time between frames The stick point is located at 7ff0h See Table 2 9 Table 2 8 VCNT_RST Initiator VCNT_RST Comments End_of_VAW 0 Default operation reset at end of VAW TRIG_DASRT or End_ of_VAW 1 Triggered termination RST_VCTAB 2 Reset from VCTAB FEN asserted or 3 Reset from start of FEN TRIG_DASRT or RST_ VCTAB 4 T...

Page 41: ...e board has a continuous data mode which is not frame oriented In continuous data mode the board will acquire data based only on the clock and data qualifying signals There are no acquisition commands in this mode See Table 2 11 Note See also Section 2 7 for more details on the how the acquisition commands work Table 2 10 VCNT_LD Initiator VCNT_LD Comments None 0 No load FEN_ASRT and ENV LOAD 1 As...

Page 42: ...e 2 13 2 6 2 Horizontal Operations and Events The horizontal operations and events are related to the horizontal axis of an image in memory or on the display or line timing of a camera The operations are mainly commands to HCOUNT Each operation can be initiated by some event The selection of the event that will initiate the specific operation is done by a set of three control bits related to each ...

Page 43: ...operation is independent from all of the others Table 2 14 Horizontal Operations Horizontal operation Control bits HCOUNT released from zero HCNT_RLS_ZERO HCOUNT reset to zero HCNT_RST HCOUNT load with 2000h HCNT_LD HCOUNT release from 1FF0h HCNT_RLS7F0 HCOUNT increment HCNT_INC Start horizontal active window HAW_START Table 2 15 Horizontal Events Event description Event Name ENCODER asserted ENC_...

Page 44: ...en it hits the stick point The pur pose of the stick point is to allow for very long periods of time between lines The stick point is located at 1ff0h See Table 2 18 Table 2 16 HCNT_RLS_ZERO Initiator HCNT_RLS_ ZERO Comments None 0 Normal operation mode no stop at zero ENC_ASRT 1 One shot mode wait for encoder for release Table 2 17 HCNT_RST Initiator HCNT_RST Comments END_OF_HAW 0 Default operati...

Page 45: ...rsion F 0 BitFlow Inc KBN 2 25 HCOUNT Load To 2000h This operation controls how and when HCOUNT loads jumps to 2000h see Table 2 19 Table 2 19 HCNT_LD Initiator HCNT_LD Comments None 0 No load LEN_ASRT 1 Load on LEN assert qualified with ENH LOAD column ENC_ASRT 2 Load on ENCODER assert qualified with ENHLOAD column ...

Page 46: ...R the selected trigger ACQ_CON a bitfield that defines special acquisition modes for the state machine The current state of the machine can be observed by the AQCMD and AQSTAT bit fields described below 2 7 1 The Acquisition Bitfields The acquisition command bits AQCMD describe the command to be performed in the next frame The acquisition status bits AQSTAT describe the current command that is per...

Page 47: ...rame Figure 2 9 shows a SNAP operation with ACQ_CON 1 In this mode after the TRIGGER has been asserted and the com mand executed the host must write a new command in the AQCMD field Figure 2 10 shows acquisition in ACQ_CON 2 mode Here as long as the GRAB command is on a frame will be acquired for every assertion of the TRIGGER In this mode there is no need for the host to write a new command Table...

Page 48: ...mand Timing Figure 2 8 Abort Command Timing Grab command written AQSTAT set grabbing starts Freeze command written AQSTAT reset grabbing ends VACTIVE AQCMD 3 AQSTAT 3 0 0 0 0 VACTIVE AQCMD 3 AQSTAT 3 0 0 0 0 1 Grab command written AQSTAT set grabbing starts Abort command written AQCMD reset AQSTAT reset grabbing ends ...

Page 49: ...Camera Control Acquisition Command and Status Version F 0 BitFlow Inc KBN 2 29 Figure 2 9 Snap Command Timing with ACQ_CON 2 Trigger asserts Snap command written AQCMD reset and AQSTAT set AQSTAT reset VACTIVE AQCMD 2 AQSTAT TRIG 2 0 0 0 0 ...

Page 50: ... Command and Status The Karbon KBN 2 30 BitFlow Inc Version F 0 Figure 2 10 Grab Command Timing with ACQ_CON 2 Trigger asserts Grab command written AQSTAT set AQSTAT reset AQSTAT set AQSTAT reset VACTIVE AQCMD AQSTAT TRIG 2 2 0 0 0 3 3 ...

Page 51: ...pturing one frame There are three possible exter nal hardware inputs to the trigger circuit and a software input Assertion of the trigger can be delayed by up to 8192 lines granularity is 8 lines This delay works only with the external hardware trigger Figure 2 11 illustrates the trigger circuit Figure 2 11 Trigger Circuit 4 1 MUX DELAY LINE TRIGGER_TTL TRIGGER_DIF TRIGGER_OPTO FEN XOR OR TRIGGER_...

Page 52: ...zontal operation for example capturing one line There are three possible exter nal hardware inputs to the encoder circuit and a software input The selected external encoder can be divided by the value in the ENC_DIV register Figure 2 12 illustrates the encoder circuit Figure 2 12 Encoder Circuit 3 1 MUX 6 2 ENCODER_TTL ENCODER_DIF ENCODER_OPTO XOR OR ENC_DIV EN_ENCODER SW_ENC ENCODER SELENC ENCPOL...

Page 53: ...enerator is set by FREE_RUN_RATE in CON17 The CLOCK_IN will be divided by the number programmed in FREE_RUN_RATE Register FREE_RUN_HI in CON17 defines the amount of CLOCK_INs that the signal will be high in a period The purpose of this register is to be able to control the duty cycle pulse width of the signal generator independent of the frequency The output of the generator can be optionally inve...

Page 54: ...On Board Signal Generator The Karbon KBN 2 34 BitFlow Inc Version F 0 Figure 2 13 Signal Generator Clock Generator Signal Generator 2 1 MUX Divide By 8K CFREQ CLOCK_IN SCALE_BY8 SIG_GEN_POL FREE_RUN_HI FREE_RUN_RATE XOR SIG_GEN ...

Page 55: ...his manual Table 3 1 Status Bits Status Bits Function and Relationship Register Details AQSTAT Acquistion status CON3 Section 4 6 FACTIVE Acquistion status vertical active CON3 Section 3 2 FCOUNT Acquistion status 3 bit frames counter CON3 Section 3 2 LCOUNT Camera status LEN is toggling CON4 Section 3 3 PCOUNT Camera status PCLK is toggling CON4 Section 3 3 FENCOUNT Camera status FEN is toggling ...

Page 56: ...It works for both area scan and line scan com eras For both line scan and area scan cameras there is always a vertical size defined by ALPF FCOUNT is a 3 bit frame counter that is incremented by the rising edge of FACTIVE It can be used to track acquisition especially in triggered modes FCOUNT works for both area scan and line scan cameras ...

Page 57: ...CLK Reading a constant value from this register indicates that the camera s clock does not reach the acquisition cir cuitry LCOUNT is a 2 bit counter clocked by the camera s LEN Reading a constant value from this register indicates that the camera s LEN does not reach the acquisition cir cuitry FENCOUNT is a 2 bit counter clocked by the camera s FEN Reading a constant value from this register indi...

Page 58: ..._ENC_DIFF TTL OPTO The Karbon KBN 3 4 BitFlow Inc Version F 0 3 4 RD_TRIG_DIFF TTL OPTO RD_ENC_DIFF TTL OPTO The level of all three trigger and all three encoder inputs can be read This helps establish connection with external industrial equipment ...

Page 59: ...the horizontal and vertical CTABs VCOUNT is the address counter of the VCTAB This register indicates the cur rent VCTAB address HCOUNT is the 2 LSB of the HCTAB address counter This register indicates only if the HCTAB is cycling Reading a constant value on HCOUNT indicates that the HCTAB address is stuck LINES_TOGO specifies how more many lines there are till the end of the frame ...

Page 60: ...er gives the 8 bit value of the video from the first eight bits of the main con nector It is helpful to determine if the camera is reacting to light Convering the cam era s lense will yield a low value in this register Pointing the camera to a light source will yield a high value in this register ...

Page 61: ...T_ADD Version F 0 BitFlow Inc KBN 3 7 3 7 DEST_ADD This register gives the DMA destination address During acquisition this register should change Reading a constant value from this register suggests that the DMA operation is not progressing ...

Page 62: ...P r e l i m i n a r y DEST_ADD The Karbon KBN 3 8 BitFlow Inc Version F 0 ...

Page 63: ...lmost all of these registers are the same There are only a few bits that are different between these two models these will be indicated in the bitfield defni tions Registers that are related to DMA operations which are different between the Neon R64 and the Karbon families have their own chapters All of the registers are 32 bits wide These wide registers are named CON0 CON1 etc Each registers is b...

Page 64: ...eded with REG_ For example the bitfield CFREQ is referred to in software as REG_CFREQ Bitfield details This section describes how the bitfield is accessed The first part describes the how the bits can be accessed For exam ple R W means the register can be both read and writen See theTable 4 2 for details The second part is the wide reg ister that the bitfield is located in In the example above thi...

Page 65: ...s Table 4 2 Abbreviations Access Meaning R W Bitfield can be read and written RO Bitfield can only be read Writing to this bit has no effect WO Bitfield can only be written Reading from this bit will return meaning less values Karbon This bitfield is functional on the Karbon Neon This bitfield is functional on the Neon R64 This bitfield is functional on the R64 family ...

Page 66: ...EN 3 CFGDONE 4 CFGCLOCK 5 FW_7MHZ 6 Reserved 7 POCL_EN 8 CFREQ 9 CFREQ 10 CFREQ 11 Reserved 12 L_CLKCON 13 L_CLKCON 14 SEL_UCLKC_7MHZ 15 RELOAD_FPGA 16 FW_SEL 17 FW_SEL 18 FW_SEL 19 CPLD_MODE 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 67: ...HZ RO CON0 5 Karbon Neon R64 If this bit is set then the board has the update Firmware which can program the fre quency of the UART clock to 7 3 MHz If this bit is zero then the board has the origo nal firmware and the UART can only be driver by an 8 MHz clock See also the bit SEL_UCLK_7MHz POCL_EN R W CON0 7 Neon New This bit turns the the PoCL Safe Power system This bit must be set to one in ord...

Page 68: ...codes are for test diagnostics SEL_UCLK_ 7MHZ R W CON0 14 Karbon Neon R64 This bit selects the frequency that is used to driver the UART for serial communica tions This functionality is only available on boards with update firmware The bit FW_ 7MHZ can be used to check the version of the firmware CFREQ Frequency 0 000b DC 1 001b 3 75 MHz 2 010b 7 5 MHz 3 011b 15 MHz 4 100b 24 MHz 5 101b 30 MHz 6 1...

Page 69: ...given type of firmware For each major type of CCD tap configuratoin there is a separate firmware file that is down loaded to the board However in some cases different manufacturers choses slightly different ways to implement the same tap configuration In these cases this bitfield is used to select between the different modes As the meaning for this bitfield differ for each firwmare file and these ...

Page 70: ...NT_RST 4 VCNT_RST 5 VCNT_RST 6 VCNT_LD 7 VCNT_LD 8 VCNT_LD 9 VCNT_RLS_STK 10 VCNT_RLS_STK 11 VCNT_RLS_STK 12 ABORT_CON 13 ABORT_CON 14 ABORT_CON 15 NO_VB_WAIT 16 ACQ_CON 17 ACQ_CON 18 ACQ_CON 19 FREEZE_CON 20 FREEZE_CON 21 FREEZE_CON 22 ACQ_SAFETY 23 NO_RULE 24 INT_CTAB 25 INT_OVSTEP 26 INT_HW 27 INT_TRIG 28 INT_SER 29 INT_QUAD 30 INT_TRIGCON 31 INT_TRIGCON ...

Page 71: ...01b Edge Mode VCOUNT sticks at zero VCOUNT is released from zero by the leading edge of the trig ger 2 010b Level Mode VCOUNT sticks at zero only if the trig ger is de asserted If trigger is asserted then VCOUNT does not stick at zero VCOUNT is released from zero by the leading edge of trigger 3 011b Reserved VCNT_RST Meaning 0 000b VCOUNT is reset by the End of Vertical Acquisition Window or by t...

Page 72: ...erties VCNT_LD Meaning 0 000b No load operation performed 1 001b VCOUNT is loaded at the assertion of FEN qualified with the ENVLOAD column in the VCTAB 2 010b VCOUNT is loaded at the assertion of FEN 3 011b VCOUNT is loaded at the assertion of trigger VCNT_RLS_STK Meaning 0 VCOUNT does not stick at 7FF0h 1 VCOUNT sticks at 7FF0h It will be released from that address by a LOAD or RESET operation A...

Page 73: ...at maximum speed regardless of wether the data is valid ACQ_CON Meaning 0 000b Acquisition is initiated by host writing the command 1 001b The acquisition command written by host will start executing at assertion of trigger triggered acquisi tion 2 010b While the GRAB command is on a frame will be acquired at the assertion of trigger 3 011b Continuous acquisition mode Host commands are ignored Dat...

Page 74: ...nabled if its corresponding mask ENINT_OVSTP has been set to 1 This interrupt can be cleared by the host writing a 0 to this location For the host to be able to write to this location the CMDWRITE code must be set to 2 INT_HW R W CON1 26 Karbon Neon R64 This interrupt will be set by a hardware exception a loss of sync or by the host writing to this bit The interrupt will be enabled if its correspo...

Page 75: ...t implements the serial communi cation protocol The interrupt will be enabled if its corresponding mask ENINT_SER has been set to 1 This interrupt can be cleared by the host writing to the UART INT_QUAD R W CON1 29 Karbon Neon R64 This interrupt will be set by a DMA QUAD or by the host writing to this bit The inter rupt will be enabled if its corresponding mask ENINT_QUAD has been set to 1 This in...

Page 76: ...31 20 Karbon Neon R64 This register controls the trigger edge that will cause an interrupt INT_TRIGCON Meaning 0 00b reserved 1 01b Assert interrupt on rising edge of trigger 2 10b Assert interrupt on falling edge of trigger 3 11b Assert interrupt on both the rising and the falling edge of the trigger ...

Page 77: ...HCNT_RLS_ZERO 3 HCNT_RST 4 HCNT_RST 5 HCNT_RST 6 HCNT_LD 7 HCNT_LD 8 HCNT_LD 9 HCNT_RLS_STK 10 HCNT_RLS_STK 11 HCNT_RLS_STK 12 RST_HVCOUNT 13 RST_DPM_ADDR 14 CTABHOLD 15 Reserved 16 CC1_CON 17 CC1_CON 18 CC1_CON 19 CC2_CON 20 CC2_CON 21 CC2_CON 22 CC3_CON 23 CC3_CON 24 CC3_CON 25 CC4_CON 26 CC4_CON 27 CC4_CON 28 CMDWRITE 29 CMDWRITE 30 CMDWRITE 31 QTBSRC ...

Page 78: ...s the loading of the HCOUNT with 2000h HCNT_RLS_ZERO Meaning 0 HCOUNT does not stop at 000h 1 HCOUNT stops at 000h It will be released by the assertion of the encoder HCNT_RST Meaning 0 000b HCOUNT will be reset by the end of the Horizontal Active Window 1 001b HCOUNT will be reset by the assertion of FEN or the HRESET from the HCTAB 2 010b HCOUNT will be reset by the HRESET in the HCTAB HCNT_LD M...

Page 79: ...Karbon Neon R64 This bit has the following properties CTABHOLD R W CON2 14 Karbon Neon R64 This bit has the following properties HCNT_RLS_STK Meaning 0 HCOUNT will not stick at 1FF0h 1 HCOUNT will stick at 1FF0h It will be released by a load or reset command RST_HVCOUNT Meaning 0 Normal operation for HCOUNT VCOUNT 1 Reset HCOUNT VCOUNT RST_DPM_ADDR Meaning 0 Normal operation for DPM_ADDR 1 Reset D...

Page 80: ...the signal steered to the CC2 CC1_CON Signal steered to CC1 0 000b CT0 from CTAB 1 001b CT1 from CTAB 2 010b CT2 from CTAB 3 011b Free running signal generated on board 4 100b On board generated CLOCK 5 101b GPIN0 6 110b 0 7 111b 1 CC2_CON Signal steered to CC2 0 000b CT0 from CTAB 1 001b CT1 from CTAB 2 010b CT2 from CTAB 3 011b Free running signal generated on board 4 100b On board generated CLO...

Page 81: ...tly different than the previous three CC4 can be controlled by CT3 This changes allows all four CTs to be tied to a CC CC3_CON Signal steered to CC3 0 000b CT0 from CTAB 1 001b CT1 from CTAB 2 010b CT2 from CTAB 3 011b Free running signal generated on board 4 100b On board generated CLOCK 5 101b GPIN0 6 110b 0 7 111b 1 CC4_CON Signal steered to CC4 0 000b CT0 from CTAB 1 001b CT1 from CTAB 2 010b ...

Page 82: ...ode is set that interrupt can not be asserted by its source It can be modified only by the host This mechanism allows to perform reliable read modify write cycles QTBSRC RO CON2 31 Karbon Neon R64 Always read back 1 CMDWRITE Interrupt allowed for host access 0 000b No interrupt can be accessed by host 1 001b INT_CTAB 2 010b INT_OVSTP 3 011b INT_HW 4 100b INT_TRIG 5 101b INT_QTAB 6 110b INT_EOF 7 1...

Page 83: ...ame 0 AQCMD 1 AQCMD 2 AQSTAT 3 AQSTAT 4 FACTIVE 5 FCOUNT 6 FCOUNT 7 FCOUNT 8 REV_DCC 9 REV_DCC 10 REV_DCC 11 REV_DCC 12 REV_DCC 13 REV_DCC 14 REV_DCC 15 REV_DCC 16 REV_DCC 17 REV_DCC 18 REV_DCC 19 REV_DCC 20 REV_DCC 21 REV_DCC 22 REV_DCC 23 REV_DCC 24 AUX_DETECT 25 GPIN0 26 GPIN1 27 GPIN2 28 GPIN3 29 GPIN4 30 SW 31 SW ...

Page 84: ...d FACTIVE RO CON3 4 Karbon Neon R64 FCOUNT RO CON3 7 5 Karbon Neon R64 This is a 3 bit modulo 8 counter The counter is incremented by the start of the Verti cal Acquisition Window It is used as a debug diagnostic tool REV_DCC WO CON3 23 8 Karbon Neon R64 FW revision AQCMD Meaning 0 00b FREEZE 1 01b ABORT 2 10b SNAP 3 11b GRAB AQSTAT Meaning 0 00b FREEZE 1 01b ABORT 2 10b SNAP 3 11b GRAB FACTIVE Me...

Page 85: ...er GPIN2 RO CON3 27 Karbon Neon R64 LVDS general purpose input from pins 15 16 of the IO connector The logical value applied to those pins will be reflected in this register GPIN3 RO CON3 28 Karbon Neon R64 LVDS general purpose input from pins 17 18 of the IO connector The logical value applied to those pins will be reflected in this register GPIN4 RO CON3 29 Karbon Neon R64 LVDS general purpose i...

Page 86: ...EP 2 ENINT_HW 3 ENINT_TRIG 4 ENINT_SER 5 ENINT_QUAD 6 EOF_IN_AQ 7 INT_ANY 8 ENINT_ALL 9 AUX_CAM 10 GPOUT0 11 GPOUT1 12 GPOUT2 13 GPOUT3 14 GPOUT4 15 GPOUT5 16 GPOUT6 17 RST_SER 18 OVS 19 RST_OVS 20 CL_DISABLE 21 LCOUNT 22 LCOUNT 23 PCOUNT 24 PCOUNT 25 FENCOUNT 26 FENCOUNT 27 POP_TOSS 28 PUMP_OFF 29 DMA_BUSY 30 HAW_START 31 VAW_START ...

Page 87: ...ties ENINT_HW R W CON4 2 Karbon Neon R64 This bit has the following properties ENINT_TRIG R W CON4 3 Karbon Neon R64 This bit has the following properties ENINT_CTAB Meaning 0 CTAB interrupt disabled 1 CATB interrupt enabled ENINT_OVSTEP Meaning 0 OVERSTEP interrupt disabled 1 OVERSTEP interrupt enabled ENINT_HW Meaning 0 HW interrupt disabled 1 HW interrupt enabled ENINT_TRIG Meaning 0 Trigger in...

Page 88: ...e queue before starting acquisition With this functionality enable interrupts only occur during acquisition INT_ANY RO CON4 7 Neon R64 New On the products that use the PLDA engine this bit indicates that an interrupt was emitted by the board This bit can be checked first to see if some event caused the interrupt before inquiring other bits to see the actual cause of the interrupt ENINT_ALL R W CON...

Page 89: ... outputs 26 27 on the IO connector See also CON8 for signals steered to the GPOUTs GPOUT3 R W CON4 13 Karbon Neon R64 The value written in this register will be reflected on the TTL output 28 on the IO con nector See also CON8 for signals steered to the GPOUTs GPOUT4 R W CON4 14 Karbon Neon R64 The value written in this register will be reflected on the TTL output 29 on the IO con nector See also ...

Page 90: ...normal operation this bit should always be set to 0 LCOUNT RO CON4 22 21 Karbon Neon R64 This is a 2 bit counter clocked by the LEN supplied by the Camera Link main connec tor Reading this counter and observing changes between reads indicates an active LEN RST_SER Meaning 0 UART normal operation 1 UART s reset line asserted OVS Meaning 0 No overstep occurred since this bit was cleared 1 At least o...

Page 91: ...serving changes between reads indicates an active FEN POP_TOSS R W CON4 27 R64 Karbon Neon R64 For normal operation this bit should be set to 0 It is used for high level clean up PUMP_OFF R W CON4 28 R64 Karbon Neon R64 For normal operation this bit should be set to 0 It is used for high level clean up DMA_BUSY RO CON4 29 R64 Karbon Neon R64 This bit indicates the state of the DMA engine POP_TOSS ...

Page 92: ... following properties HAW_START Meaning 0 The start of the Horizontal Active Window HAW is controlled by the start of the LEN 1 The start of the Horizontal Active Window is con trolled by the HSTART column in the HCTAB VAW_START Meaning 0 The start of the Vertical Active Window VAW is con trolled by the start of the FEN 1 The start of the Vertical Active Window is controlled by the VSTART column i...

Page 93: ...SELENC 6 ENCPOL 7 SW_ENC 8 RD_TRIG_DIFF 9 RD_TRIG_TTL 10 RD_TRIG_OPTO 11 RD_ENC_DIFF 12 RD_ENC_TTL 13 RD_ENC_OPTO 14 TRIGGER_DELAY 15 TRIGGER_DELAY 16 TRIGGER_DELAY 17 TRIGGER_DELAY 18 TRIGGER_DELAY 19 TRIGGER_DELAY 20 TRIGGER_DELAY 21 TRIGGER_DELAY 22 TRIGGER_DELAY 23 TRIGGER_DELAY 24 ENINT_EOF 25 INT_EOF 26 RD_FEN 27 CCSYNC 28 CCSYNC 29 CCSYNC 30 EN_TRIGGER 31 EN_ENCODER ...

Page 94: ... the SW trigger SEL_TRIG Meaning 0 00b The trigger used by the board is the differential trig ger on the IO connector 1 01b The trigger used by the board is the TTL trigger on the IO connector 2 10b The trigger used by the board is the opto coupled trigger on the IO connector 3 11b The FEN signal on the CL1 connector will be used as trigger When this mode is used the register FEN POL is used to co...

Page 95: ... Neon R64 This register reflects the status of the differential trigger input on the IO connector pins 1 2 RD_TRIG_TTL RO CON5 9 Karbon Neon R64 This register reflects the status of the TTL trigger input on the IO connector pin 3 SELENC Meaning 0 00b The encoder used by the board is the differential encoder on the IO connector 1 01b The encoder used by the board is the TTL encoder on the IO connec...

Page 96: ... the status of the opto coupled encoder input on the IO connec tor pins 10 11 TRIGGER_DELAY R W CON5 23 14 Karbon Neon R64 The number N written in this register will delay the trigger by 8N lines ENINT_EOF R W CON4 24 Karbon Neon R64 This bitfield has the following properties INT_EOF R W CON4 25 Karbon Neon R64 This interrupt will be set by the acquisition state machine at the end of the frame end...

Page 97: ...R64 This bitfield has the following properties INT_TRIG Meaning 0 No interrupt from end of frame 1 Interrupt from end of frame CCSYNC Meaning 0 000b CCs are not synchronized 1 001b CCs are synchronized to the pixel clock of the pri mary camera 2 010b CCs are synchronized to the pixel clock of the sec ondary camera 3 011b Each set of CCs are synchronized to the pixel clock of their corresponding ca...

Page 98: ...ter The Karbon KBN 4 36 BitFlow Inc Version F 0 EN_ENCODER R W CON5 31 Karbon Neon R64 This bitfield has the following properties EN_ENCODER Meaning 0 External HW selected encoder is disabled 1 External HW selected encoder is enabled ...

Page 99: ... 0 VCOUNT 1 VCOUNT 2 VCOUNT 3 VCOUNT 4 VCOUNT 5 VCOUNT 6 VCOUNT 7 VCOUNT 8 VCOUNT 9 VCOUNT 10 VCOUNT 11 VCOUNT 12 VCOUNT 13 VCOUNT 14 VCOUNT 15 VCOUNT 16 VCOUNT 17 LAL 18 ENC_DIV 19 ENC_DIV 20 ENC_DIV 21 ENC_DIV 22 ENC_DIV 23 ENC_DIV 24 ENC_DIV 25 ENC_DIV 26 ENC_DIV 27 ENC_DIV 28 HCOUNT 29 HCOUNT 30 Reserved 31 Reserved ...

Page 100: ...own by the number written in this register If for example ENC_DIV 5 for every five pulses on the selected encoder the divider will supply one pulse to the board Programming this register to 0 or 1 will both divide by 1 HCOUNT R W CON6 29 28 Karbon Neon R64 This register reflects the current value of the two LSBs of the HCOUNT Reading this register and observing changes in its value means that the ...

Page 101: ...UNT 3 AQ_COUNT 4 AQ_COUNT 5 AQ_COUNT 6 AQ_COUNT 7 AQ_COUNT 8 AQ_COUNT 9 AQ_COUNT 10 AQ_COUNT 11 AQ_COUNT 12 AQ_COUNT 13 AQ_COUNT 14 AQ_COUNT 15 AQ_COUNT 16 AQ_COUNT 17 AQ_COUNT 18 AQ_COUNT 19 AQ_COUNT 20 SEL_REG_GEN 21 SEL_REG_GEN 22 GEN_ONESHOT 23 Reserved 24 TAG_BANK 25 TAG_BANK 26 TAG_BANK 27 TAG_BANK 28 TAG_BANK 29 TAG_BANK 30 Reserved 31 Reserved ...

Page 102: ...FREEZE_CON code must be set to 1 SEL_REG_GEN R W CON7 21 20 Karbon Neon R64 New GEN_ONESHOT R W CON7 22 R64 New This bit controls the mode of the special signal generator available in the TVI camera specific firmware TAG_BANK RO CON7 29 24 R64 This is the calculated bank from the address generator latched by the TAG QUAD diagnostics test register GEN_ONESHOT Meaning 0 Signal generator is free runn...

Page 103: ...GPOUT1_CON 5 GPOUT1_CON 6 GPOUT2_CON 7 GPOUT2_CON 8 GPOUT2_CON 9 GPOUT3_CON 10 GPOUT3_CON 11 GPOUT3_CON 12 GPOUT4_CON 13 GPOUT4_CON 14 GPOUT4_CON 15 GPOUT5_CON 16 GPOUT5_CON 17 GPOUT5_CON 18 GPOUT6_CON 19 GPOUT6_CON 20 GPOUT6_CON 21 Reserved 22 Reserved 23 Reserved 24 RLE_LOAD_H 25 RLE_LOAD_H 26 RLE_LOAD_H 27 RLE_LOAD_H 28 RLE_LOAD_V 29 RLE_LOAD_V 30 RLE_LOAD_V 31 RLE_LOAD_V ...

Page 104: ...rom CTAB 4 100b CT3 from CTAB 5 101b Internally generated CLOCK frequency controlled by CFREQ in CON1 6 110b Internally generated signal frequency and duty cycle controlled by CON17 7 111b The encoder input signal is routed to the GPOUT0 output signal GPOUT1_CON Selected signal steered to GPOUT1 0 000b GPOUT1 bit written by host in CON4 1 001b CT0 from CTAB 2 010b CT1 from CTAB 3 011b CT2 from CTA...

Page 105: ...in CON4 1 001b CT0 from CTAB 2 010b CT1 from CTAB 3 011b CT2 from CTAB 4 100b CT3 from CTAB 5 101b Internally generated CLOCK frequency controlled by CFREQ in CON1 6 110b Internally generated signal frequency and duty cycle controlled by CON17 7 111b reserved GPOUT3_CON Selected signal steered to GPOUT3 0 000b GPOUT3 bit written by host in CON4 1 001b CT0 from CTAB 2 010b CT1 from CTAB 3 011b CT2 ...

Page 106: ...4 1 001b CT0 from CTAB 2 010b CT1 from CTAB 3 011b CT2 from CTAB 4 100b CT3 from CTAB 5 101b Internally generated CLOCK frequency controlled by CFREQ in CON1 6 110b Internally generated signal frequency and duty cycle controlled by CON17 7 111b reserved GPOUT5_CON Selected signal steered to GPOUT5 0 000b GPOUT5 bit written by host in CON4 1 001b CT0 from CTAB 2 010b CT1 from CTAB 3 011b CT2 from C...

Page 107: ...register should be pro grammed to 3 RLE_LOAD_V R W CON8 31 28 Karbon Neon New For boards that use RLE CTabs this register controls the location that the vertical RLE counter jumps to when the FEN signal is asserted The units of value in this bitfield is RLE entry not the CTAB location In other words if the jump point is 0x20000 CTAB location but the RLE entry for this location is 3 then this regis...

Page 108: ...2 MUX_REV 3 MUX_REV 4 MUX_REV 5 MUX_REV 6 MUX_REV 7 MUX_REV 8 MUX_REV 9 MUX_REV 10 MUX_REV 11 MUX_REV 12 TRIM 13 TRIM 14 TRIM 15 TRIM 16 FW_TYPE 17 FW_TYPE 18 FW_TYPE 19 FW_TYPE 20 DISPLAY 21 CLIP 22 SHORT_FRAME 23 RST_CALC_BANK 24 CALC_BANK 25 CALC_BANK 26 CALC_BANK 27 CALC_BANK 28 CALC_BANK 29 CALC_BANK 30 ACPL_MUL 31 ACPL_MUL ...

Page 109: ...ps This bit field has the opposite effect of the DELAY field in CON14 FW_TYPE RO CON9 19 16 Karbon Neon R64 Firmware type DISPLAY R W CON9 20 Karbon Neon R64 This bit controls the acquisition of data that is more than 8 bits pixel When this bit is set only the 8 LSB of the data will be acquired in each lane To be able to display the 8 MSB or any other consecutive group of 8 bits the data must be s...

Page 110: ...displaying gray level images on VGA monitors set in 256 colors mode The upper and lower 15 gray levels are dedicated to Windows graphics SHORT_FRAME R W CON9 22 Karbon Neon R64 Future use RST_CALC_ BANK R W CON9 23 Karbon Neon R64 For normal operation this bit should be 0 CALC_BANK RO CON9 29 24 Karbon Neon R64 Value of the current calculated starting bank DISPLAY Meaning 0 Acquire full bit depth ...

Page 111: ... R W CON9 31 30 Karbon Neon R64 This register is used to increase the maximum line size the board can acquire The settings act as muliplier for the ACPL Active Clocks Per Line register ACPL_MUL Meaning 0 00b Normal operation ACPL is used as is 1 01b ACPL is multiplied by 2 2 10b Reserved 3 11b Reserved ...

Page 112: ... 0 ACPL 1 ACPL 2 ACPL 3 ACPL 4 ACPL 5 ACPL 6 ACPL 7 ACPL 8 ACPL 9 ACPL 10 ACPL 11 ACPL 12 ACPL 13 ACPL 14 ACPL 15 ACPL 16 ACPL 17 FORMAT 18 FORMAT 19 FORMAT 20 FORMAT 21 FORMAT 22 VID_SOURCE 23 VID_SOURCE 24 VID_SOURCE 25 VID_SOURCE 26 PIX_DEPTH 27 PIX_DEPTH 28 PIX_DEPTH 29 PIX_DEPTH 30 PIX_DEPTH 31 FORCE_8BIT ...

Page 113: ... identified in the camera file by the FORMAT FORMAT Firmware Name Format Description 0 00000b MUX 1 tap cameras 1 00001b MUX_2TOEP 2 taps odd even pixels 2 00010b MUX_2TOEL 2 taps odd even lines 3 00011b MUX_2TS 2 taps segmented 4 00100b MUX_2TS1RI 2 taps segmented right inverted 5 00101b MUX_4TS 4 taps segmented 6 00110b MUX_4T2S2RIOEP 4 taps odd even pixels right taps inverted 7 00111b MUX_4TQ2R...

Page 114: ... 19 10011b MUX_1TI 1 tap inverted 20 10100b MUX_8WI 8 taps 8 way interleaved 21 10101b MUX_BAY_2TS_RI Bayer decoder 2 taps segmented right inverted FORMAT Firmware Name Format Description VID_SOURCE Video source 0 0000b Camera 1 0001b Camera special mode for cameras that do not assert the VALID signal 2 0010b reserved 3 0011b Synthetic horizontal static wedge 4 0100b Synthetic dynamic wedge 5 0101...

Page 115: ...its RGB DMAed as 32 bits display mode is 24 bits 8 1000b 3x12 bits RGB DMAed as 48 bits packed display mode is 24 bits 9 1001b 32 bits 10 1010b 64 bits 11 1011b 3x8 bits RGB DMAed as 32 bits upper MSB set to 00h 12 1100b 3x8 bits RGB DMAed as 24 bits packed 13 1101b 3x10 BGR DMAed as 32 bits display mode is 24 bits 14 1110b 3x12 BGR DMAed as 48 bits packed display mode is 24 bits PIX_DEPTH Bit pix...

Page 116: ... 4 ALAST_ADD 5 ALAST_ADD 6 ALAST_ADD 7 ALAST_ADD 8 ALAST_ADD 9 ALAST_ADD 10 ALAST_ADD 11 ALAST_ADD 12 ALAST_ADD 13 ALAST_ADD 14 ALAST_ADD 15 Reserved 16 BLAST_ADD 17 BLAST_ADD 18 BLAST_ADD 19 BLAST_ADD 20 BLAST_ADD 21 BLAST_ADD 22 BLAST_ADD 23 BLAST_ADD 24 BLAST_ADD 25 BLAST_ADD 26 BLAST_ADD 27 BLAST_ADD 28 BLAST_ADD 29 BLAST_ADD 30 BLAST_ADD 31 UART_MASTER ...

Page 117: ...ON11 14 0 Karbon Neon R64 Last address for lane A used for diagnostics BLAST_ADD RO CON11 30 16 Karbon Neon R64 Last address for lane B used for diagnostics UART_MASTER R W CON11 31 Karbon New This bit controls which Karbon VFG is in control of the UART Poke this bit to one in order to take control of the UART ...

Page 118: ...D 4 CLAST_ADD 5 CLAST_ADD 6 CLAST_ADD 7 CLAST_ADD 8 CLAST_ADD 9 CLAST_ADD 10 CLAST_ADD 11 CLAST_ADD 12 CLAST_ADD 13 CLAST_ADD 14 CLAST_ADD 15 Reserved 16 DLAST_ADD 17 DLAST_ADD 18 DLAST_ADD 19 DLAST_ADD 20 DLAST_ADD 21 DLAST_ADD 22 DLAST_ADD 23 DLAST_ADD 24 DLAST_ADD 25 DLAST_ADD 26 DLAST_ADD 27 DLAST_ADD 28 DLAST_ADD 29 DLAST_ADD 30 DLAST_ADD 31 Reserved ...

Page 119: ...trol Registers CON12 Register Version F 0 BitFlow Inc KBN 4 57 CLAST_ADD RO CON11 14 0 Karbon Neon R64 Last address for lane C used for diagnostics DLAST_ADD R W CON11 30 16 Karbon Neon R64 Last address for lane D used for diagnostics ...

Page 120: ...K 5 VIDEO_MASK 6 VIDEO_MASK 7 VIDEO_MASK 8 VIDEO_MASK 9 VIDEO_MASK 10 VIDEO_MASK 11 VIDEO_MASK 12 VIDEO_MASK 13 VIDEO_MASK 14 VIDEO_MASK 15 VIDEO_MASK 16 VIDEO_MASK 17 VIDEO_MASK 18 VIDEO_MASK 19 VIDEO_MASK 20 VIDEO_MASK 21 VIDEO_MASK 22 VIDEO_MASK 23 VIDEO_MASK 24 VIDEO_MASK 25 VIDEO_MASK 26 VIDEO_MASK 27 VIDEO_MASK 28 VIDEO_MASK 29 VIDEO_MASK 30 VIDEO_MASK 31 VIDEO_MASK ...

Page 121: ...0 BitFlow Inc KBN 4 59 VIDEO_MASK R W CON13 31 0 Karbon Neon R64 With the aid of this mask individual bits in the video data stream can be set to 0 The 32 bit mask is duplicated for the 32 MSB of a 64 bit word Bit N in VIDEO_MASK Meaning 0 Set bit N to 0 1 Pass bit N as is ...

Page 122: ...ENPOL 3 BUTTONS 4 BUTTONS 5 BUTTONS 6 BUTTONS 7 BUTTONS 8 BUTTONS 9 BUTTONS 10 BUTTONS 11 BUTTONS 12 BUTTONS 13 BUTTONS 14 BUTTONS 15 BUTTONS 16 SHIFT_RAW 17 SHIFT_RAW 18 SHIFT_RAW 19 SHIFT_RAW 20 SHIFT_RAW_LEFT 21 DELAY 22 DELAY 23 DELAY 24 SWAP 25 UART_CON 26 UART_CON 27 Reserved 28 DPM_SPLIT 29 DPM_SPLIT 30 DPM_SPLIT 31 DPM_SPLIT ...

Page 123: ...tfield has the following properties BUTTONS R W CON14 15 3 Karbon Neon R64 R W register for test diagnostics SHIFT_RAW R W CON14 19 16 Karbon Neon R64 This register defines for the barrel shifter the amount of shift for the data to be acquired SW_RESET Meaning 0 Reset de asserted 1 General reset to acquisition circuitry FENPOL Meaning 0 FEN is asserted on rising edge 1 FEN is asserted on falling e...

Page 124: ...f the CTABs is 8 clocks so both DELAY and the CTABS may have to be used in together to accommodate for some delays The net effect for a simple one tap camera will be a shifting to the right of the dis played image For multi tap cameras the visual effect is more complex and depends on the taps architecture All taps are delayed by the same amount The purpose of this bit field is to align the image p...

Page 125: ...to the DPM UART_CON Connection 0 00b On board UART connected to CL serial port of main connector 1 01b On board UART connected to CL serial port of auxil iary connector 2 10b Serial port of main connector CL connected to exter nal serial port through the IO connector 3 11b Serial port of auxiliary connector CL connected to external serial port through the IO connector DPM_SPLIT Mode 0 0000b Normal...

Page 126: ... 6 FREE_RUN_RATE 7 FREE_RUN_RATE 8 FREE_RUN_RATE 9 FREE_RUN_RATE 10 FREE_RUN_RATE 11 FREE_RUN_RATE 12 FREE_RUN_RATE 13 FREE_RUN_RATE 14 FREE_RUN_RATE 15 FREE_RUN_RATE 16 FREE_RUN_HI 17 FREE_RUN_HI 18 FREE_RUN_HI 19 FREE_RUN_HI 20 FREE_RUN_HI 21 FREE_RUN_HI 22 FREE_RUN_HI 23 FREE_RUN_HI 24 FREE_RUN_HI 25 FREE_RUN_HI 26 FREE_RUN_HI 27 FREE_RUN_HI 28 FREE_RUN_HI 29 FREE_RUN_HI 30 FREE_RUN_HI 31 FREE_...

Page 127: ...e frequency is pro grammed in CON0 Programming the FREE_RUN_RATE to 200 for example will yield a signals whose period is 200 clocks FREE_RUN_HI R W CON17 31 16 Karbon Neon R64 This register defines the amount of time the free running generator is 1 during a period Setting this register to 100 for example will yield a signal that is 1 for 100 clocks regardless of the period Obviously the number pro...

Page 128: ...t Name 0 ALPF 1 ALPF 2 ALPF 3 ALPF 4 ALPF 5 ALPF 6 ALPF 7 ALPF 8 ALPF 9 ALPF 10 ALPF 11 ALPF 12 ALPF 13 ALPF 14 ALPF 15 ALPF 16 ALPF 17 TOP_REV 18 TOP_REV 19 TOP_REV 20 TOP_REV 21 TOP_REV 22 TOP_REV 23 TOP_REV 24 TOP_REV 25 TOP_REV 26 TOP_REV 27 TOP_REV 28 TOP_REV 29 TOP_REV 30 SIG_GEN_POL 31 SCALE_BY8K ...

Page 129: ...o grammed with the value 200 as for every LEN the camera supplies two lines TOP_REV RO CON9 11 0 Karbon Neon R64 Firmware revision SIG_GEN_POL R W CON18 30 Karbon Neon R64 This bit allows for the inversion of the free running generator s output SCALE_BY8K R W CON18 31 Karbon Neon R64 Scaling down the clock to the free running generator can yield waveforms on the order of single Hz SIG_GEN_POL Mean...

Page 130: ...OGO 4 LINES_TOGO 5 LINES_TOGO 6 LINES_TOGO 7 LINES_TOGO 8 LINES_TOGO 9 LINES_TOGO 10 LINES_TOGO 11 LINES_TOGO 12 LINES_TOGO 13 LINES_TOGO 14 LINES_TOGO 15 LINES_TOGO 16 LINES_TOGO 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 131: ... y Camera Control Registers CON19 Register Version F 0 BitFlow Inc KBN 4 69 LINES_TOGO R W CON19 16 0 Karbon Neon R64 This register will reflect the number of remaining lines left to be acquired till the end of the frame ...

Page 132: ...FIFO_EQ 5 FIFO_EQ 6 FIFO_EQ 7 FIFO_EQ 8 VID_BRL 9 VID_BRL 10 VID_BRL 11 VID_BRL 12 VID_BRL 13 VID_BRL 14 VID_BRL 15 VID_BRL 16 VIDEO_2DPM 17 VIDEO_2DPM 18 VIDEO_2DPM 19 VIDEO_2DPM 20 VIDEO_2DPM 21 VIDEO_2DPM 22 VIDEO_2DPM 23 VIDEO_2DPM 24 COLOR_MASK 25 COLOR_MASK 26 SHIFT_DSP_SELECT 27 SHIFT_DSP 28 SHIFT_DSP 29 SHIFT_DSP 30 SHIFT_DSP 31 SHIFT_DSP_LEFT ...

Page 133: ...for diagnostics test COLOR_MASK R W CON20 25 24 Karbon Neon R64 This bitfield can be used to mask out color channels when acquiring color pixels for mats e g 24 bit color 36 bit color etc SHIFT_DSP_ SELECT R W CON20 26 Karbon Neon R64 This bitfield has the following properties SHIFT_DISP R W CON20 30 27 Karbon Neon R64 This register holds the shift amount for data to be displayed COLOR_MASK Meanin...

Page 134: ... CON20 Register The Karbon KBN 4 72 BitFlow Inc Version F 0 SHIFT_DSP_LEFT R W CON20 31 Karbon Neon R64 This bitfield has the following properties SHIFT_DSP_LEFT Meaning 0 Shift display data right 1 Shift display data left ...

Page 135: ...wnloaded to the board Bit Name 0 RED_GAIN 1 RED_GAIN 2 RED_GAIN 3 RED_GAIN 4 RED_GAIN 5 RED_GAIN 6 RED_GAIN 7 RED_GAIN 8 GREEN_GAIN 9 GREEN_GAIN 10 GREEN_GAIN 11 GREEN_GAIN 12 GREEN_GAIN 13 GREEN_GAIN 14 GREEN_GAIN 15 GREEN_GAIN 16 BLUE_GAIN 17 BLUE_GAIN 18 BLUE_GAIN 19 BLUE_GAIN 20 BLUE_GAIN 21 BLUE_GAIN 22 BLUE_GAIN 23 BLUE_GAIN 24 DECODER_OUT 25 DECODER_OUT 26 DECODER_OUT 27 Reserved 28 BAYER_B...

Page 136: ...ed down by 64 Numbers above 255 are clipped to 255 saturation effect BLUE_GAIN R W CON21 23 16 Karbon R64 This register controls the gain of the blue channel The video value is multiplied by the value in BLUE_GAIN and after that scaled down by 64 Numbers above 255 are clipped to 255 saturation effect DECODER_OUT R W CON21 26 24 Karbon R64 These bits controls the output of the Bayer decoder DECODER...

Page 137: ...HASE R W CON21 31 30 Karbon R64 These bits control the starting phase of the Bayer decoder This register is set based on the arragement of the color matrix in the camera s CCD BAYER_10_BIT Meaning 0 00b 8 bit pixels 1 01b 12 bit pixels 2 10b 10 bit pixels 3 11b Reserved DECODER_PHASE Meaning 0 00b First two pixels Blue Green 1 01b First two pixels Green Blue 2 10b First two pixels Red Green 3 11b ...

Page 138: ...E 5 DPM_SIZE 6 DPM_SIZE 7 DPM_SIZE 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 CTAB_INT_CON 16 LINES_PER_INT 17 LINES_PER_INT 18 LINES_PER_INT 19 LINES_PER_INT 20 LINES_PER_INT 21 LINES_PER_INT 22 LINES_PER_INT 23 LINES_PER_INT 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 139: ...e CTAB interrupt LINES_PER_INT RW CON23 23 16 Karbon Neon New This bit controls the lines per interrup circuit This circuit can be used to create a peri odic interrupt on the CTAB interrupt The interrupt rate will be every N lines where N is the value programmed in this register Note that CTAB_INT_CON must be set to one in order for the interrupts to be seen by the host CTAB_INT_CON Meaning 0 CTAB...

Page 140: ...A 1 LUT_HOST_DATA 2 LUT_HOST_DATA 3 LUT_HOST_DATA 4 LUT_HOST_DATA 5 LUT_HOST_DATA 6 LUT_HOST_DATA 7 LUT_HOST_DATA 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 LUT_ON 16 LUT_HOST_ADDR 17 LUT_HOST_ADDR 18 LUT_HOST_ADDR 19 LUT_HOST_ADDR 20 LUT_HOST_ADDR 21 LUT_HOST_ADDR 22 LUT_HOST_ADDR 23 LUT_HOST_ADDR 24 LUT_BANK 25 LUT_BANK 26 Reserved 27 LUT_DATA_WRITE_ SEL...

Page 141: ...e LUT_HOST_DATA register to the LUT s memory location as specified by LUT_HOST_ADDR The procedure to read data from the LUT is as follows Set LUT_HOST_ACCESS to 1 Set LUT_DATA_WRITE_SEL to 0 Set LUT_BANK to the desired bank to read Set LUT_HOST_LANE to the desired LUT lane to read Set LUT_HOST_ADDR to the desired LUT location to read Read LUT_HOST_DATA the value returned in this register is the va...

Page 142: ...WRITE_SEL is set to 0 writing to this bit has no effect See LUT_HOST_DATA for more information LUT_BANK Meaning 0 000b Host access to bank 0 data passes through bank 0 1 001b Host access to bank 1 data passes through bank 1 2 010b Host access to bank 2 data passes through bank 2 3 011b Host access to bank 3 data passes through bank 3 LUT_DATA_WRITE_SEL Meaning 0 When reading LUT_HOST_DATA the regi...

Page 143: ...ters CON24 Register Version F 0 BitFlow Inc KBN 4 81 LUT_HOST_ ACCESS R W CON24 31 Karbon R64 These bits turns on and off host access to the LUT DECODER_OUT Meaning 0 The LUT cannot be accessed by the host 1 The LUT can be accessed by the host ...

Page 144: ...1 3 DELAY_TAP1_SEL 4 Reserved 5 Reserved 6 Reserved 7 Reserved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 145: ...o the DELAY register DELAY_TAP1_ SEL R W CON25 3 Karbon Neon R64 This bit selects the register that controls the delay for tap 1 Tap 0 is always controlled by the register DELAY DELAY_TAP1 Meaning 0 000b HAW is not delayed 1 001b HAW is delayed by 1 clocks 2 010b HAW is delayed by 2 clocks 3 011b HAW is delayed by 3 clocks 4 100b HAW is delayed by 4 clocks 5 101b HAW is delayed by 5 clocks 6 11ob ...

Page 146: ...d 3 Reserved 4 Reserved 5 Reserved 6 Reserved 7 Reserved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 147: ...Reserved 3 Reserved 4 Reserved 5 Reserved 6 Reserved 7 Reserved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 148: ... 4 MEM_ADDR_LO 5 MEM_ADDR_LO 6 MEM_ADDR_LO 7 MEM_ADDR_LO 8 MEM_ADDR_LO 9 MEM_ADDR_LO 10 MEM_ADDR_LO 11 MEM_ADDR_LO 12 MEM_ADDR_LO 13 MEM_ADDR_LO 14 MEM_ADDR_LO 15 MEM_ADDR_LO 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 149: ...rol Registers CON36 Register Version F 0 BitFlow Inc KBN 4 87 MEM_ADDR_LO R W CON25 15 0 Neon New This register is the lower 16 bits used to access the flash or ROM memory on boards that have it This is not a user programmable register ...

Page 150: ..._HI 3 MEM_ADDR_HI 4 MEM_CS 5 MEM_WRITE 6 DWNLD_MODE 7 DWNLD_MODE 8 MEM_DATA 9 MEM_DATA 10 MEM_DATA 11 MEM_DATA 12 MEM_DATA 13 MEM_DATA 14 MEM_DATA 15 MEM_DATA 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 151: ... controls both reading and writing to either the flash or the ROM This bit controls both host access and FPGA download source This is not a user programmable register MEM_WRITE R W CON37 5 Neon New DWNLD_MODE R W CON37 7 6 Neon New MEM_DATA R W CON37 15 8 Neon New This bitfield provides data access used when reading or writting the flash or ROM on boards that support these features This is not a u...

Page 152: ... 3 Reserved 4 POCL_SENSE 5 POCL_CLK_ DETECTED 6 POCL_DETECTED 7 Reserved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 153: ... state machine will immedi ately remove the power if it sense that the pixel clock has stopped POCL_SENSE RO CON38 3 Neon New This register indicates that the PoCL state machine is the sense state In this state the powers has not been applied and the PoCL state machine is watching the impen dence on the CL cable If the impendence of a PoCL camera is detected the power will be applied It a short is...

Page 154: ...ed state This state is the normal powered up steady state for the PoCL state machine POCL_ DETECTED RO CON38 6 Neon New This register indicates that the PoCL state machine has detected a PoCL camera POCL_SENSE Meaning 0 The PoCL state machine is not in the sense state 1 The PoCL state machine is in the sense state POCL_CLK_DETECTED Meaning 0 The PoCL state machine has not detected a camera pixel c...

Page 155: ...ntroduction Version F 0 BitFlow Inc KBN 5 1 Karbon Neon DMA Registers Chapter 5 5 1 Introduction This section enumerates all of the registers that control DMA on boards using the PLDA DMA engine e g Karbon CL The formatting is explained in Section 4 2 ...

Page 156: ..._LO 9 FIRST_QUAD_PTR_LO 10 FIRST_QUAD_PTR_LO 11 FIRST_QUAD_PTR_LO 12 FIRST_QUAD_PTR_LO 13 FIRST_QUAD_PTR_LO 14 FIRST_QUAD_PTR_LO 15 FIRST_QUAD_PTR_LO 16 FIRST_QUAD_PTR_LO 17 FIRST_QUAD_PTR_LO 18 FIRST_QUAD_PTR_LO 19 FIRST_QUAD_PTR_LO 20 FIRST_QUAD_PTR_LO 21 FIRST_QUAD_PTR_LO 22 FIRST_QUAD_PTR_LO 23 FIRST_QUAD_PTR_LO 24 FIRST_QUAD_PTR_LO 25 FIRST_QUAD_PTR_LO 26 FIRST_QUAD_PTR_LO 27 FIRST_QUAD_PTR_L...

Page 157: ...FIRST_QUAD_ PTR_LO R W CON28 31 0 Karbon Neon This is the low word of the 64 bit address of the first DMA scatter gather instruction in a chain of instructions This register can be written at any time but the DMA engine only loads this value when byte count as set by CHAIN_DATA_SIZE goes to zero ...

Page 158: ..._HI 9 FIRST_QUAD_PTR_HI 10 FIRST_QUAD_PTR_HI 11 FIRST_QUAD_PTR_HI 12 FIRST_QUAD_PTR_HI 13 FIRST_QUAD_PTR_HI 14 FIRST_QUAD_PTR_HI 15 FIRST_QUAD_PTR_HI 16 FIRST_QUAD_PTR_HI 17 FIRST_QUAD_PTR_HI 18 FIRST_QUAD_PTR_HI 19 FIRST_QUAD_PTR_HI 20 FIRST_QUAD_PTR_HI 21 FIRST_QUAD_PTR_HI 22 FIRST_QUAD_PTR_HI 23 FIRST_QUAD_PTR_HI 24 FIRST_QUAD_PTR_HI 25 FIRST_QUAD_PTR_HI 26 FIRST_QUAD_PTR_HI 27 FIRST_QUAD_PTR_H...

Page 159: ...FIRST_QUAD_ PTR_HI R W CON29 31 0 Karbon Neon This is the high word of the 64 bit address of the first DMA scatter gather instruction in a chain of instructions This register can be written at any time but the DMA engine only loads this value when byte count as set by CHAIN_DATA_SIZE goes to zero ...

Page 160: ...8 CHAIN_DATA_SIZE 9 CHAIN_DATA_SIZE 10 CHAIN_DATA_SIZE 11 CHAIN_DATA_SIZE 12 CHAIN_DATA_SIZE 13 CHAIN_DATA_SIZE 14 CHAIN_DATA_SIZE 15 CHAIN_DATA_SIZE 16 CHAIN_DATA_SIZE 17 CHAIN_DATA_SIZE 18 CHAIN_DATA_SIZE 19 CHAIN_DATA_SIZE 20 CHAIN_DATA_SIZE 21 CHAIN_DATA_SIZE 22 CHAIN_DATA_SIZE 23 CHAIN_DATA_SIZE 24 CHAIN_DATA_SIZE 25 CHAIN_DATA_SIZE 26 CHAIN_DATA_SIZE 27 CHAIN_DATA_SIZE 28 CHAIN_DATA_SIZE 29 ...

Page 161: ...amount of data in the chain in bytes The value in this register is loaded into the DMA engine when DMA is initiated This value is then decremented every DMA transfer When the count reached zero this value in this register is reloaded into the DMA engine and the first scatter gather instruction pointed to by FIRST_QUAD_PTR_HI and FIRST_QUAD_PTR_LO is loaded ...

Page 162: ...8 CHAIN_DATA_TOGO 9 CHAIN_DATA_TOGO 10 CHAIN_DATA_TOGO 11 CHAIN_DATA_TOGO 12 CHAIN_DATA_TOGO 13 CHAIN_DATA_TOGO 14 CHAIN_DATA_TOGO 15 CHAIN_DATA_TOGO 16 CHAIN_DATA_TOGO 17 CHAIN_DATA_TOGO 18 CHAIN_DATA_TOGO 19 CHAIN_DATA_TOGO 20 CHAIN_DATA_TOGO 21 CHAIN_DATA_TOGO 22 CHAIN_DATA_TOGO 23 CHAIN_DATA_TOGO 24 CHAIN_DATA_TOGO 25 CHAIN_DATA_TOGO 26 CHAIN_DATA_TOGO 27 CHAIN_DATA_TOGO 28 CHAIN_DATA_TOGO 29 ...

Page 163: ...r e l i m i n a r y Karbon Neon DMA Registers CON31 Register Version F 0 BitFlow Inc KBN 5 9 CHAIN_DATA_ TOGO RO CON31 31 0 Karbon Neon This register indicates the number of bytes remaining the DMA chain ...

Page 164: ...MA_STATUS 5 DMA_STATUS 6 DMA_STATUS 7 DMA_STATUS 8 DMA_NO_RULE 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 DMA_INIT_FUNC 17 DMA_PRIORITY 18 DMA_64_BIT 19 DMA_CHAINING 20 DMA_COMMAND 21 DMA_COMMAND 22 DMA_COMMAND 23 DMA_COMMAND 24 DMA_BEN 25 DMA_BEN 26 DMA_BEN 27 DMA_BEN 28 LATCH_CONTROL 29 LATCH_CONTROL 30 Reserved 31 Reserved ...

Page 165: ...is indicates the status of the DMA engine DMA_STATUS RO CON32 7 4 Karbon Neon Current status of the DMA engine Do we want to add a table DMA_NO_RULE R W CON32 8 Karbon Neon Setting this bit to a 1 will cause the DMA engine to DMA data as fast as it can It will not wait for data to be available from the acquisition engine The actual data that is DMAed will be unpredictable This bit therefore is onl...

Page 166: ...4_BIT R W CON3 18 Karbon Neon Controls where the DMA operations are 64 bit or 32 bit DMA_CHAINING RW CON32 19 Karbon Neon This bit determines whether the DMA engine will execute chaining DMA or not DMA_ COMMAND R W CON32 23 20 Karbon Neon DMA_BEN R W CON32 27 24 Karbon Neon LATCH_ CONTROL R W CON32 29 28 Karbon Neon DMA_64_BIT Meaning 0 1 DMA_CHAINING Meaning 0 1 ...

Page 167: ...XFR_PER_INT 6 XFR_PER_INT 7 XFR_PER_INT 8 XFR_PER_INT 9 XFR_PER_INT 10 XFR_PER_INT 11 XFR_PER_INT 12 XFR_PER_INT 13 XFR_PER_INT 14 XFR_PER_INT 15 XFR_PER_INT 16 XFR_PER_INT 17 XFR_PER_INT 18 XFR_PER_INT 19 XFR_PER_INT 20 XFR_PER_INT 21 XFR_PER_INT 22 XFR_PER_INT 23 XFR_PER_INT 24 XFR_PER_INT 25 XFR_PER_INT 26 XFR_PER_INT 27 XFR_PER_INT 28 XFR_PER_INT 29 XFR_PER_INT 30 XFR_PER_INT 31 XFR_PER_INT ...

Page 168: ...ister The Karbon KBN 5 14 BitFlow Inc Version F 0 XFR_PER_INT R W CON33 31 0 Karbon Neon This register controls how often the board issues an EOF interupt Every time XFR_ PER_INT bytes have been DMAed the board will emit an interrupt ...

Page 169: ...ing Introduction Version F 0 BitFlow Inc KBN 6 1 Register and Memory Mapping Chapter 6 6 1 Introduction This section explains how the registers and the various chunks of memory are mapped and accessed on the Karbon CL and its virtual frame grabbers ...

Page 170: ...t wide The DPM can be accessed as 64 bit on 64 bit boundary or as 32 bit wide on 32 bit boundary memory During acquisition GRAB SNAP the slave read from DPM is inhibited In this case data read will be always zero 6 2 4 TAG At the start and the end of every frame there is an 8 byte long TAG quad The source address of the TAG is irrelevant as there is no data read The destination is a special trash ...

Page 171: ...y 00 10 00 08 CON11 nnnnyyyy 00 10 00 10 CON12 nnnnyyyy 00 10 00 18 CON13 nnnnyyyy 00 10 00 20 CON14 nnnnyyyy 00 10 00 28 CON15 nnnnyyyy 00 00 00 08 CON16 nnnnyyyy 00 00 00 10 CON17 nnnnyyyy 00 00 00 18 CON18 nnnnyyyy 00 00 00 20 CON19 nnnnyyyy 00 00 00 28 CON20 nnnnyyyy 00 10 00 30 CON21 nnnnyyyy 00 10 00 38 Board version dependent CON22 nnnnyyyy 00 00 00 30 CON23 nnnnyyyy 00 00 00 38 Board versi...

Page 172: ...ord n not used y used All registers are treated as 64 bit wide The Karbon uses two BARs for PCI access BAR0 memory mapped 1M size is used for access to QL5064 internal regis ters BAR1 memory mapped 16M size is used for access to R64 registers CTABs DPM The Karbon uses address lines 23 to 3 Pre fetch and posting WRITEs are disabled for both BARs ...

Page 173: ...or download and the full interface will be done on the fly according to the destination address The mechanics of the download assertion of CLOCK DATA CONFIG etc is beyond the scope of this manual There are only two FPGAs to download MUX and DCC The MUX is downloaded first Different types of firmware types can be downloaded for different applications The board has been designed to handle different ...

Page 174: ...formation The Karbon KBN 6 6 BitFlow Inc Version F 0 6 5 PCI Configuration Space and Model Revision Information All Karbon boards will have the same device ID Information about different models and board capabilities will be stored in the INFO_HI and INFO_LO registers ...

Page 175: ...by Scatter Gather DMA instructions These called quads because they generally consist of four words although the Karbon s DMA engine only uses three words A list of instructions are called a Quad Table or QTAB Each quad consists of the following entries 1 Destination address 2 Size of transfer 3 Next quad address The following sections document the structure of these quads ...

Page 176: ...4 Destination Address 13 Destination Address 45 Destination Address 14 Destination Address 46 Destination Address 15 Destination Address 47 Destination Address 16 Destination Address 48 Destination Address 17 Destination Address 49 Destination Address 18 Destination Address 50 Destination Address 19 Destination Address 51 Destination Address 20 Destination Address 52 Destination Address 21 Destina...

Page 177: ... Data Size 4 Data Size 5 Data Size 6 Data Size 7 Data Size 8 Data Size 9 Data Size 10 Data Size 11 Data Size 12 Data Size 13 Data Size 14 Data Size 15 Data Size 16 Data Size 17 Data Size 18 Data Size 19 Data Size 20 Data Size 21 Data Size 22 Data Size 23 Data Size 24 Data Size 25 Data Size 26 Data Size 27 Data Size 28 Data Size 29 Data Size 30 Data Size 31 Data Size ...

Page 178: ...ad Address 44 Next Quad Address 13 Next Quad Address 45 Next Quad Address 14 Next Quad Address 46 Next Quad Address 15 Next Quad Address 47 Next Quad Address 16 Next Quad Address 48 Next Quad Address 17 Next Quad Address 49 Next Quad Address 18 Next Quad Address 50 Next Quad Address 19 Next Quad Address 51 Next Quad Address 20 Next Quad Address 52 Next Quad Address 21 Next Quad Address 53 Next Qua...

Page 179: ...ectrical Interfacing Chapter 7 7 1 Introduction This chapter describes the electrical interface of the Karbon Neon R64 This includes detailed information on the all if the input and output signals In addition information is provided on recommend circuits to use when connecting to these signals ...

Page 180: ... unselected triggers will have no effect on the board However they can be used as general purpose inputs 7 2 2 The Optocoupled Trigger The opto coupled trigger allows the acquisition circuitry to accept a trigger signal without having a galvanic connection to the trigger source This is mandatory in some medical and industrial application The trigger information is passed as a light pulse from an o...

Page 181: ...l Interfacing Trigger Version F 0 BitFlow Inc KBN 7 3 Figure 7 1 Driver Circuit for Opto Coupled Trigger 5V 5V TRIG G ER_O PTO _A P3 Pin 5 TRIG G ER_O PTO _K P3 Pin 4 7407 3 3K User Cir c uit O pt o Co upl er PC3H711 TRIG G ER_O PTO ...

Page 182: ...ve no effect on the board However they can be used as general purpose inputs 7 3 2 The Optocoupled Encoder The opto coupled encoder allows the acquisition circuitry to accept an encoder sig nal without having a galvanic connection to the encoder source This is mandatory in some medical and industrial application The encoder information is passed as a light pulse from an on board LED that is couple...

Page 183: ...lectrical Interfacing Encoder Version F 0 BitFlow Inc KBN 7 5 Figure 7 2 Driver Circuit for Opto Coupled Encoder 5V 5V ENCODER_OPTO_A P3 Pin 11 ENCODER_OPTO_K P3 Pin 10 7407 3 3K User Circuit Opto Coupler PC3H711 ENCODER_OPTO ...

Page 184: ...eneral Purpose Inputs GPIN There are five general purpose inputs The signal level on each input can be read on the corresponding GPIN bit The electrical characteristic of these inputs is shown in the following list GPIN0 GPIN1 Single ended TTL level inputs GPIN2 GPIN3 GPIN4 Differential LVDS inputs ...

Page 185: ... in CON8 The source for each GPOUT can be programmed independently of the others Table 7 1 shows the sources for each GPOUT 7 5 1 The Open Collector Drivers for GPOUT5 and GPOUT6 GPOUT5 and GPOUT6 are open collector drivers Figure 7 3 shows the GPOUT5 and GPOUT6 driver circuits and their associated jumpers for various configurations how to handle difference between boards The board is shipped in w...

Page 186: ... 8 BitFlow Inc Version F 0 Figure 7 3 Driver Circuits for GPOUT5 and GPOUT6 in Default Configuration GPOUT5 JP2 JP1 12V 5V GPOUT5_VCC P3 Pin 32 GPOUT5_OC P3 Pin 31 7407 1K 220 680 GPOUT6 JP4 JP3 12V 5V GPOU6_VCC P3 Pin 42 GPOUT6_OC P3 Pin 33 7407 1K 220 680 1 2 3 1 2 3 ...

Page 187: ...he board s open collector GPOUT5 can drive an user s opto coupled device configured for galvanic isolation between the board and the user The power to the user s LED is supplied by the board s 5V through a 220 Ohm resistor This is achieved by inserting the short in position 1 2 at JP1 The jumper at JP2 is removed The open collector driver will sink the current from the LED There is no gal vanic co...

Page 188: ...Outputs GPOUT The Karbon KBN 7 10 BitFlow Inc Version F 0 Figure 7 5 GPOUT5 Driving Opto Coupled Circuit using Galvanic Isolation GPOUT5 JP2 JP1 12V 5V GPOUT5_VCC P3 Pin 32 GPOUT5_OC P3 Pin 31 7407 1K 220 680 User Circuit Opto Coupler 1 2 3 ...

Page 189: ...e source for each CC is controlled by the corresponding CCx_CON bitfield Table 7 2 illus trates the source for each CCx as a function of its associated CCx_CON bitfield Table 7 2 CCx_CON CCx_CON CCx Source 0 000b CT0 from CTAB 1 001b CT1 from CTAB 2 010b CT2 from CTAB 3 011b Free running on board signal generator Controlled by FREE_RUN_RATE and FREE_ RUN_HIGH 4 100b Internally generated clock Freq...

Page 190: ...P r e l i m i n a r y Camera Link Controls CCs The Karbon KBN 7 12 BitFlow Inc Version F 0 ...

Page 191: ...and x16 Slot size Maximum Input Pixel Clock Frequency 85 MHz Minimum Input Pixel Clock Frequency 20 MHz Maximum Pixels Per Line 1 tap 262 144 256K Pixels Section 8 2 Maximum Lines Per Frame 131 072 128K Lines Section 8 3 Minimum clocks between lines 4 Clocks Minimum lines between frames 0 Lines Minimum pixel clocks between frames 4 Clocks Minimum trigger pulse 600 Nanoseconds Minimum encoder pulse...

Page 192: ...by the following formula Max_pix_per_line 256K x Taps Taps is the number of taps A tap supplies a whole pixel Examples A two tap camera that supplies odd even pixels Max_pix_per_line 512K An RGB camera that supplies RGB over 24 bits Max_pix_per_line 256K as every clock the camera supplies one single pixel A four tap two segments each left right Max_pix_per_line 1M ...

Page 193: ...mum number of lines per frame is given by the follow ing formula Max_lines_per_frame 128K x Line_taps Line_taps is the number of taps that supply a whole line Examples A one tap camera Max_lines_per_frame 128K A two tap camera that supplies odd even lines Max_lines_per_frame 256K A two tap camera that supplies odd even pixels Max_lines_per_frame 128K ...

Page 194: ...P r e l i m i n a r y Power Consumption The Karbon KBN 8 4 BitFlow Inc Version F 0 8 4 Power Consumption ...

Page 195: ...L4 which consists of the main board plus the aux iliary board The primary purpose of the auxiliary board is to hold the third and fourth Camera Link connectors This board does not need to be in a PCI Express slot In fact it does not require any power from the PC and can be located in any slot that is not used The mechanical layout of the Karbon CL main board is shown in Figure 9 1 The mechanical l...

Page 196: ...P r e l i m i n a r y Introduction The Karbon KBN 9 2 BitFlow Inc Version F 0 Figure 9 2 Karbon Auxiliary Board Layout CL3 CL4 Jumper Set 3 P12 P13 P14 ...

Page 197: ...tor 4 P12 Auxiliary Connector 1 P13 Auxiliary Connector 2 P14 Auxiliary Connector 3 Figure 9 2 shows the locations of these connectors 9 2 1 The CL Connectors The CL connectors are for connecting Camera Link cameras Table 9 1 illustrates how to connect the Karbon to various types and numbers of Camera Link Cameras Also for each camera the Virtual Frame Grabber VFG that the camera will be connected...

Page 198: ...ing sections 9 2 3 The Auxiliary Connectors The auxiliary connectors P1 P2 and P3 are used to connect the main board to the auxiliary board connectors P12 P13 and P14 respectively The connectors are are dif ferent sizes to avoid incorrect pairing One Medium Camera Camera 1 Connector 1 VFG0 Camera 1 Connector 2 VFG0 Two Medium Cameras Camera 1 Connector 1 VFG0 Camera 1 Connector 2 VFG0 Camera 2 Con...

Page 199: ...9 3 1 Jumpers Figure 9 3 shows the detailed structure of the jumpers Figure 9 3 Karbon CL Jumpers Jumper fields JP2 JP3 JP4 and JP5 control the configuration of the open collector GPOUT5 and GPOUT6 See Section 7 5 1 on GPOUT5 and GPOUT6 configuration Jumper fields JP10 and JP11 on the main board and JP1 and JP2 on the auxiliar board are not user configurable They are set at the factory in conjunct...

Page 200: ...Volt connected to GPOUT5_VCC through a 680 Ohm resistor Power disconnected from GPOUT5_VCC factory default JP3 1K pull up resistor installed between GPOUT5_OC and GPOUT5_VCC fac tory default N A No pull up on GPOUT5 JP4 5 Volt connected to GPOUT6_VCC through a 220 Ohm resistor 12 Volt connected to GPOUT6_VCC through a 680 Ohm resistor Power disconnected from GPOUT6_VCC factory default JP5 1K pull ...

Page 201: ...more than one board in a system The idea is to set the switches differently on each board in the system The switch settings can be read for each board from software by reading the SW bitfield SysReg also shows the switch setting for each board See Table 9 5 below shows the switch set tings and the corresponding value in the SW bitfield Table 9 5 Switch Setting S1 S2 SW register down down 0 down up...

Page 202: ...era Link spec ification for frame grabbers This specification is maintained by the Automated Imag ing Association Please contact this organization for a copy of the specification At the time of this printing it is available on the web at www machinevisiononline org It is important to understand that some of these signals are the output of a high speed serial converter chip and require special inst...

Page 203: ...IGGER LVDS 2 In VFG0_TRIGGER LVDS 3 In VFG0_TRIGGER_TTL TTL 4 In VFG0_TRIGGER_OPTO_K Cathode of optocoupling sensor 5 In VFG0_TRIGGER_OPTO_A Anode of optocoupling sensor 6 GND 7 In VFG0_ENCODER LVDS 8 In VFG0_ENCODER LVDS 9 In VFG0_ENCODER_TTL TTL 10 In VFG0_ENCODER_OPTO_K Cathode of optocoupling sensor 11 In VFG0_ENCODER_OPTO_A Anode of optocoupling sensor 12 GND 13 In VFG0_GPIN0_TTL TTL 14 In VF...

Page 204: ...smit line 38 GND 39 In SIN_RS232 RS232 receive line 40 GND 41 In VFG1_TRIGGER LVDS 42 In VFG1_TRIGGER LVDS 43 In VFG1_TRIGGER_TTL TTL 44 In VFG1_ENCODER LVDS 45 In VFG1_ENCODER LVDS 46 In VFG1_ENCODER_TTL TTL 47 In VFG2_TRIGGER LVDS 48 In VFG2_TRIGGER LVDS 49 In VFG2_TRIGGER_TTL TTL 50 In VFG2_ENCODER LVDS 51 In VFG2_ENCODER LVDS 52 In VFG2_ENCODER_TTL TTL 53 In VFG3_TRIGGER LVDS 54 In VFG3_TRIGGE...

Page 205: ...4 28 CLAST_ADD KBN 4 57 CLIP KBN 4 48 CMDWRITE KBN 4 20 CON0 KBN 4 4 CON1 KBN 4 8 CON10 KBN 4 50 CON11 KBN 4 54 CON12 KBN 4 56 CON13 KBN 4 58 CON14 KBN 4 60 CON17 KBN 4 64 CON18 KBN 4 66 CON19 KBN 4 68 CON2 KBN 4 15 CON20 KBN 4 70 CON21 KBN 4 73 CON23 KBN 4 76 CON24 KBN 4 78 CON25 KBN 4 82 CON26 KBN 4 84 CON27 KBN 4 85 CON28 KBN 5 2 CON29 KBN 5 4 CON3 KBN 4 21 CON30 KBN 5 6 CON31 KBN 5 8 CON32 KBN...

Page 206: ...EE_RUN_HI KBN 4 65 FREE_RUN_RATE KBN 4 65 FREEZE_CON KBN 4 11 FW_7MHZ KBN 4 5 FW_SEL KBN 4 7 FW_TYPE KBN 4 47 G GEN_ONESHOT KBN 4 40 General Purpose Inputs GPIN KBN 7 6 General Purpose Outputs GPOUT KBN 7 7 GPIN0 KBN 4 23 GPIN1 KBN 4 23 GPIN2 KBN 4 23 GPIN3 KBN 4 23 GPIN4 KBN 4 23 GPOUT0 KBN 4 27 GPOUT0_CON KBN 4 42 GPOUT1 KBN 4 27 GPOUT1_CON KBN 4 42 GPOUT2 KBN 4 27 GPOUT2_CON KBN 4 43 GPOUT3 KBN...

Page 207: ...S KBN 4 29 PUMP_OFF KBN 4 29 Q QTBSRC KBN 4 20 R R W KBN 4 3 RD_ENC_DIFF KBN 4 34 KBN 4 35 RD_ENC_OPTO KBN 4 34 RD_ENC_TTL KBN 4 34 RD_TRIG_DIFF KBN 4 33 RD_TRIG_OPTO KBN 4 34 RD_TRIG_TTL KBN 4 33 REG_GAIN KBN 4 74 RELOAD_FPGA KBN 4 7 REV_DCC KBN 4 22 RLE_LOAD_H KBN 4 45 RLE_LOAD_V KBN 4 45 RO KBN 4 3 RST_CALC_BANK KBN 4 48 RST_DPM_ADDR KBN 4 17 RST_HVCOUNT KBN 4 17 RST_OVS KBN 4 28 RST_SER KBN 4 ...

Page 208: ... UART_MASTER KBN 4 55 V VAW_START KBN 4 30 VCNT_LD KBN 4 10 VCNT_RLS_STK KBN 4 10 VCNT_RLS_ZERO KBN 4 9 VCNT_RST KBN 4 9 VCOUNT KBN 4 38 VFG KBN 1 1 VID_BRL KBN 4 71 VID_SOURCE KBN 4 52 VIDEO_2DPM KBN 4 71 VIDEO_MASK KBN 4 59 W WO KBN 4 3 X XFR_PER_INT KBN 5 14 ...

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