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BUF_MGR_TIMEOUT

The Cyton-CXP

CYT-3-10

BitFlow, Inc.

Version A.0

QUAD_
COMPLETE_
TIMEOUT

R/W, BUF_MGR_TIMEOUT[15..0], Cyton-CXP

The maximum amount of time to wait for a Quad completion. Units are 4 nanosec-
onds. Writable only when BM_STATE is Idle.

DISABLE_
TIMEOUT

R/W, BUF_MGR_TIMEOUT[31], Cyton-CXP

Setting this bit to 1 will disable the Quad completion timeout mechanism. The Buffer
Manager will wait an infinite amount of time for a Quad completion to return. For
debug only. Writable only when BM_STATE is Idle.

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Summary of Contents for Cyton-CXP

Page 1: ...The Cyton CXP Hardware Reference Manual BitFlow Inc 400 West Cummings Park Suite 5050 Woburn MA 01801 USA Tel 781 932 2900 Fax 781 933 9965 Email support bitflow com Web www bitflow com Revision A 0 ...

Page 2: ... implicit warranty for the use of its products and assumes no responsibility for any errors that may appear in this document nor does it make a commit ment to update the information contained herein BitFlow Inc retains the right to make changes to these specifications at any time without notice All trademarks are properties of their respective holders Revision History Revision Date Comments Pre 20...

Page 3: ...rs CYT 1 6 Up Link CYT 1 6 Cyton CXP I O system CYT 1 7 The Timing Sequencer Signal Generator CYT 1 7 The Volume Of Interest Acquisition Engine CYT 1 7 The StreamSync System CYT 1 7 CoaXPress Power CYT 1 8 The Routing of CXP Links to VFGs CYT 1 9 The BitFlow CXP Models CYT 1 10 2 The StreamSync Acquisition Engine Introduction CYT 2 1 The StreamSync Acquisition Engine World CYT 2 2 Controlling the ...

Page 4: ...ync Buffer Manager Introduction CYT 3 1 The Buffer Manager Details CYT 3 2 CON485 Register CYT 3 3 CON486 Register CYT 3 5 BUF_MGR_CON CYT 3 7 BUF_MGR_TIMEOUT CYT 3 9 BOARD_CONFIG CYT 3 11 PACKETS_SENT_STATUS CYT 3 13 QUADS_USED_STATUS CYT 3 15 QTABS_USED_STATUS CYT 3 17 PKT_STAT CYT 3 19 QUADS_LOADED_STATUS CYT 3 22 QTABS_LOADED_STATUS CYT 3 24 BUF_MGR_STATUS CYT 3 26 PKT_CON CYT 3 29 4 Timing Se...

Page 5: ...ON22 Register CYT 5 12 CON51 Register CYT 5 14 6 Encoder Divider Introduction CYT 6 1 Encoder Divider Details CYT 6 2 Formula CYT 6 2 Example CYT 6 2 Restrictions CYT 6 2 PLL Locking CYT 6 3 Handling Encoder Slow Down or Stopping CYT 6 3 Encoder Divider Control Registers CYT 6 4 7 Karbon Cyton CXP I O System Registers Introduction CYT 7 1 CON60 CYT 7 2 CON61 CYT 7 4 CON62 CYT 7 6 CON63 CYT 7 10 CO...

Page 6: ...143 CYT 8 63 CON147 CYT 8 65 CON148 CYT 8 67 CON149 CYT 8 70 CON150 CYT 8 73 CON152 CYT 8 76 CON153 CYT 8 78 CON154 CYT 8 80 CON155 CYT 8 82 CON158 CYT 8 84 CON159 CYT 8 86 CON160 CYT 8 88 CON163 CYT 8 90 CON168 CYT 8 92 CON169 CYT 8 95 CON170 CYT 8 97 CON171 CYT 8 99 CON172 CYT 8 101 CON173 CYT 8 103 CON174 CYT 8 105 CON175 CYT 8 107 CON179 CYT 8 109 CON180 CYT 8 111 CON181 CYT 8 114 CON182 CYT 8...

Page 7: ...YT 8 182 CON358 CYT 8 184 CON360 CYT 8 186 CON361 CYT 8 188 CON363 CYT 8 190 CON372 CYT 8 192 CON428 CYT 8 194 9 Electrical Interfacing Introduction CYT 9 1 Trigger CYT 9 2 Trigger Input Types CYT 9 2 The Optocoupled Trigger CYT 9 2 Encoder CYT 9 4 Encoder Input Types CYT 9 4 The Optocoupled Encoder CYT 9 4 General Purpose Inputs GPIN CYT 9 6 Introduction CYT 9 6 R64 GPIN Configuration CYT 9 6 Neo...

Page 8: ...rivers CYT 9 10 Camera Link Controls CCs CYT 9 13 10 Mechanical Introduction CYT 10 1 The Cyton CXP Connectors CYT 10 2 The CXP Connectors CYT 10 2 Switches CYT 10 3 LEDs CYT 10 5 CXP Downlink LED Meaning CYT 10 6 CXP Uplink LED Meaning CYT 10 6 Button CYT 10 7 The Auxilary Power Connector P4 CYT 10 8 The I O Box Connector P1 CYT 10 9 I O Connector Pinout for the Cyton CXP CYT 10 10 ...

Page 9: ...b site is www bitflow com Technical support is available at 781 932 2900 from 9 00 AM to 6 00 PM Eastern Stan dard Time Monday through Friday For technical support by email support bitflow com or by FAX 781 933 9965 please include the following Product name Camera type and mode being used Software revision number Computer CPU type PCI chipset bus speed Operating system Example code if applicable P...

Page 10: ... are used for numerical notation in this manual Table P 2 shows the numerical abbreviations that are used in this manual Table P 1 Base Abbreviations Base Designator Example Binary b 1010b Decimal None 4223 Hexidecimal h 12fah Table P 2 Numeric Abbreviations Abbreviation Value Example K 1024 256K M 1048576 1M ...

Page 11: ...d with REG_ For example the bitfield CFREQ is referred to in software as REG_CFREQ Bitfield details This section describes how the bitfield is accessed The first part describes the how the bits can be accessed For exam ple R W means the register can be both read and writen See theTable P 4 for details The second part is the wide reg ister that the bitfield is located in In the example above this b...

Page 12: ...ng to this bit has no effect WO Bitfield can only be written Reading from this bit will return meaningless values Karbon CL This bitfield is functional only the Karbon CL Karbon CXP This bitfield is functional only the Karbon CXP Neon This bitfield is functional only the Neon R64 This bitfield is functional only the R64 family Alta This bitfield is functional only the Alta family Cyton CXP This bi...

Page 13: ...tform this chapter is a good example While other chapters discuss the details of the virtual frame grabbers VFG that this hard ware platform supports The concept of the virtual frame grabber is described below but basically the idea is that one hardware platform can support more than one device In the case of the Cyton CXP these devices are frame grabbers Note that we are not using the word virtua...

Page 14: ... a frame grabber by making changes to its firmware is not new BitFlow has been doing this since its very first product However unique to BitFlow products is the fact the entire frame grabber is written in firmware The only fixed hardware components are the interfaces to the outside world e g the interface chips on the front end Everything else that makes up the board camera control data buff ering...

Page 15: ...mmand Packet Control CXP Data Packet Router CXP Transciever SERDES PCI Express Bus CXP Connector 3 CXP Connector 4 CXP Connector 1 CXP Connector 2 Acquitision Engine Control I O 0 Acquitision Engine Control I O 1 Acquitision Engine Control I O 2 Acquitision Engine Control I O 3 PCI Interface Buffer Manager 0 PCI Interface Buffer Manager 1 PCI Interface Buffer Manager 2 PCI Interface Buffer Manager...

Page 16: ...Firmware Camera Files and Downloads The Cyton CXP CYT 1 4 BitFlow Inc Version A 0 1 2 Firmware Camera Files and Downloads TBD ...

Page 17: ...ots The Cyton CXP is extremely flexible Each VFG can acquire from any of the CXP links on the board although certain restriction usually apply In addition each VFG can acquire from one or more CXP links This flexibility means that for example the Cyton CXP can be used as two VFGs each acquiring from a dual link CXP camera or one VFG acquiring from a quad link CXP camera in this case the other VFGs...

Page 18: ...nd assemble raster format lines 1 3 2 Command and Control Packets The second type of packet coming from the camera is a control packet When the board sees a control packet it unwraps the packet and sends the contents into a con trol data FIFO The host then reads and decodes this FIFO Currently as of CoaXPress specification 1 1 control packets are synchronous This means that the camera will only se...

Page 19: ...new timing exactly synchronized See sec tion 4 1 for more information 1 3 7 The Volume Of Interest Acquisition Engine The Cyton CXP introduces the concept of Volume of Interest VOI as part of its StreamSync Acquisition Engine This has been designed from the ground up to satisfy the needs of real world machine vision application The VOI provide robust and flexi ble programming that can handle of a ...

Page 20: ...o indicated The Cyton CXP automatically powers up all links that need power i e correctly responde to the sense circuit This happens as soon as the system is booted The Cyton CXP constantly monitors the current on each CXP link if either over current or under current conditions exist the power will be turned off The monitoring system is purely in hardware so no host computer intervention is requir...

Page 21: ...ook confusing but all of the routing details are handle automatically by software there is no need to worry about programming the routing tables manu ally in your software However it is helpful to understand the underlying structure of the Cyton Note In certain situations a VFG may have no CXP links routed to it as they may all be used by other VFGs In this case the VFG with no links can not be us...

Page 22: ...N PCE CXP4 CYT PC2 CXP4 CYT PC2 CXP4 Number of 3 125 Gb S links supported 2 4 4 2 Number of 6 25 Gb S links supported 2 0 4 2 Number of dual link cameras supported 1 2 2 1 Number of quad link cameras supported 0 1 1 0 Number of Virtual Frame Grabbers supported 2 4 4 2 Number of independent trigger inputs 2 4 4 2 Number of independent encoder inputs 2 4 4 2 Number of PCI configurations devices 2 4 ...

Page 23: ...e the StreamSync system is compatible with the previous BitFlow products However digging deeper these new system have a lot more power and flexibility These new features will be described in the following sections The StreamSync system has many improvements over previous systems The main improvements are Efficient support for variable sized images with fast context switches between frames Per fram...

Page 24: ...e Z window i e number of frames per volume is con trolled by the Z_SIZE register Finally the size of the V window i e number of volumes to acquire is controlled by the V_SIZE register Note that the size of the Y window and the Z window can be dynamically controlled by external triggers see below for more details 2 2 1 Controlling the StreamSync Acquisition Engine Acquisition of images is controlle...

Page 25: ...es the run level moves to the state above If the window at the top level closes the run level goes to idle Figure 2 2 illustrates this type of state machine Figure 2 2 Acquisition Engine Run Level The action that causes a window to be opened or closed depends on the type of win dow Some windows can be opened in more than one way For example the Y win dow can be opened when a Start Of Frame SOF pac...

Page 26: ... SOF and X window with the SOL This means that all packets from the camera will be dropped until the SOF is seen causing the Acquisition Engine to open the Y window and then packets are further dropped until SOL must be seen opening the X window Each line requires an SOL packet This process keeps the Acquisition Engine synchronize to the camera even if packets are dropped This functionality can be...

Page 27: ...larly there is a Z_OFFS register which if non zero can cause the board to discard a certain number of frames before starting an acquisition of a sequence This concept is illustrated in Figure 2 4 Figure 2 4 Z_OFFS Illustration Camera s Frame X_SIZE Y_SIZE X_OFFS Y_OFFS Acquired ROI Y Window Camera Frames Z Window V Window X Window Z_OFFS Z_SIZE ...

Page 28: ...used to start the acquisition of each frame and or end the acquisition of each frame Further a trigger could be use to start the acquisition of each volume sequence of frames and or end the acquisition of a volume Further flexibility comes from the fact that the source for each event i e open or close can be different or the same This means a frame could started with one trigger or ended with anot...

Page 29: ...ms and the newer Acquisition Engine However for users that desire more flexibility and are willing to do some lower level code the Acquisition Engine can handle almost any acquisition scenario For users who were already doing some lower level programming using other BitFlow products it s helpful to see how this new system relates to the tradition acquisition engine Table 2 2 shows some examples of...

Page 30: ...EL 4 Reserved 5 Reserved 6 Reserved 7 Reserved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 31: ...and not the current status The abort run levels exit acquisition on a clean boundary V exits on a volume boundary Z on a frame boundary Y on a line boundary X on a 128 byte data boundary AE_RUN_LEVEL Meaning 0 0000b System is idle 1 0001b Run start running i e acquiring 2 0010b Abort V stop at the end of the next volume 3 0011b Abort Z stop at the end of the next frame 4 0100b Abort Y stop at the ...

Page 32: ...IFO_OVERFLOW 5 Reserved 6 Reserved 7 Reserved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 33: ...ng table shows the meanings of each state AE_FIFO_ OVERFLOW RO AE_STATUS 4 Cyton CXP If this bit is 1 the FIFO between acquisition engine and packet generation over flowed The acquisition engine will abort AE_STATE Meaning 0 000b Idle System is idle 1 001b System is inside the V window 2 010b System is inside the Z window 3 011b System is inside the Y window 4 100b System is inside the X window ...

Page 34: ...TREAM_SEL 5 STREAM_SEL 6 STREAM_SEL 7 STREAM_SEL 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 USE_SYNTHETIC_FRAME ...

Page 35: ...quisition Engine AE_STREAM_SEL Version A 0 BitFlow Inc CYT 2 13 STREAM_SEL R W AE_STREAM_SEL 7 0 Cyton CXP TBD USE_ SYNTHETIC_ FRAME R W AE_STREAM_SEL 31 Cyton CXP Use the Synthetic Frame generator instead of the camera ...

Page 36: ..._SIZE 4 V_SIZE 5 V_SIZE 6 V_SIZE 7 V_SIZE 8 V_SIZE 9 V_SIZE 10 V_SIZE 11 V_SIZE 12 V_SIZE 13 V_SIZE 14 V_SIZE 15 V_SIZE 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 37: ... the V window that is the number of volumes to acquire A value of 0XFFFF means infinite When set to infinite the acquisition engine can be stopped by writing AE_RUN_LEVEL The most common setting for this field is either 1 or 0xFFFF This register is writable only when AE_STATE is 0 idle Writes to this field will be ignored if AE_STATE is not 0 ...

Page 38: ... Z_CLOSE_TRIG_SEL 6 Z_CLOSE_TRIG_SEL 7 Z_CLOSE_TRIG_SEL 8 Z_CLOSE 9 Z_CLOSE 10 Z_CLOSE 11 Z_CLOSE 12 Z_OPEN_TRIG_FUNC 13 Z_OPEN_TRIG_FUNC 14 Z_OPEN_TRIG_FUNC 15 Z_OPEN_TRIG_FUNC 16 Z_OPEN_TRIG_SEL 17 Z_OPEN_TRIG_SEL 18 Z_OPEN_TRIG_SEL 19 Z_OPEN_TRIG_SEL 20 Z_OPEN 21 Z_OPEN 22 Z_OPEN 23 Z_OPEN 24 Z_SYNC 25 Z_SYNC 26 Z_SYNC 27 Z_SYNC 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 39: ...uire If trigger mode is specified the trigger is selected by Z_CLOSE_TRIG_SEL and the conditioning function is specified by Z_CLOSE_TRIG_FUNC The acquisition engine waits for the trigger condition to be satisfied then continues acquiring to the next frame boundary it then closes the Z window and then checks to see if there are more volumes to acquire Z_OPEN_TRIG_ FUNC R W Z_WIN_CON 15 12 Cyton CXP...

Page 40: ...cted by Z_OPEN_TRIG_SEL and the con ditioning function is specified by Z_OPEN_TRIG_FUNC The acquisition engine waits for the trigger condition to be satisfied opens the Z window then starts the setup of the Y window Z_SYNC R W Z_WIN_CON 27 24 Cyton CXP This field enforces the data synchronization of streaming video to the acquisition engine for each individual frame in the z window The following t...

Page 41: ..._SIZE 1 Z_SIZE 2 Z_SIZE 3 Z_SIZE 4 Z_SIZE 5 Z_SIZE 6 Z_SIZE 7 Z_SIZE 8 Z_SIZE 9 Z_SIZE 10 Z_SIZE 11 Z_SIZE 12 Z_SIZE 13 Z_SIZE 14 Z_SIZE 15 Z_SIZE 16 Z_OFFS 17 Z_OFFS 18 Z_OFFS 19 Z_OFFS 20 Z_OFFS 21 Z_OFFS 22 Z_OFFS 23 Z_OFFS 24 Z_OFFS 25 Z_OFFS 26 Z_OFFS 27 Z_OFFS 28 Z_OFFS 29 Z_OFFS 30 Z_OFFS 31 Z_OFFS ...

Page 42: ...of frames Y windows to acquire per sequence Z windows The acquisition of frames will only start after Z_OFFS frames have been skipped after the Z window is opened Z_OFFS R W Z_WIN_DIM 31 16 Cyton CXP The number of frames Y windows to skip before starting acquisition after the Z win dow has been opened ...

Page 43: ..._TRIG_SEL 5 Y_CLOSE_TRIG_SEL 6 Y_CLOSE_TRIG_SEL 7 Y_CLOSE_TRIG_SEL 8 Y_CLOSE 9 Y_CLOSE 10 Y_CLOSE 11 Y_CLOSE 12 Y_OPEN_TRIG_FUNC 13 Y_OPEN_TRIG_FUNC 14 Y_OPEN_TRIG_FUNC 15 Y_OPEN_TRIG_FUNC 16 Y_OPEN_TRIG_SEL 17 Y_OPEN_TRIG_SEL 18 Y_OPEN_TRIG_SEL 19 Y_OPEN_TRIG_SEL 20 Y_OPEN 21 Y_OPEN 22 Y_OPEN 23 Y_OPEN 24 Y_SYNC 25 Y_SYNC 26 Y_SYNC 27 Y_SYNC 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 44: ... trigger mode is specified the trigger is selected by Y_CLOSE_TRIG_SEL and the conditioning function is specified by Y_CLOSE_TRIG_FUNC The acquisition engine waits for the trigger condition to be satisfied then continues acquiring to the next line boundary it then closes the Y window and then checks to see if there are more frames to acquire Y_OPEN_TRIG_ FUNC R W Y_WIN_CON 15 12 Cyton CXP This reg...

Page 45: ...ger is selected by Y_OPEN_TRIG_SEL and the con ditioning function is specified by Y_OPEN_TRIG_FUNC The acquisition engine waits for the trigger condition to be satisfied opens the Y window then starts the setup of the X window Y_SYNC R W Y_WIN_CON 27 24 Cyton CXP This field enforces the data synchronization of streaming video to the acquisition engine for each individual line in the y window The f...

Page 46: ...SIZE 2 Y_SIZE 3 Y_SIZE 4 Y_SIZE 5 Y_SIZE 6 Y_SIZE 7 Y_SIZE 8 Y_SIZE 9 Y_SIZE 10 Y_SIZE 11 Y_SIZE 12 Y_SIZE 13 Y_SIZE 14 Y_SIZE 15 Y_SIZE 16 Y_OFFS 17 Y_OFFS 18 Y_OFFS 19 Y_OFFS 20 Y_OFFS 21 Y_OFFS 22 Y_OFFS 23 Y_OFFS 24 Y_OFFS 25 Y_OFFS 26 Y_OFFS 27 Y_OFFS 28 Y_OFFS 29 Y_OFFS 30 Y_OFFS 31 Y_OFFS ...

Page 47: ...DIM 15 0 Cyton CXP Number of lines per frame Y window to acquire This number is only acquired after the Y window is opened and after Y_OFFS lines have been skipped Y_OFFS R W Y_WIN_DIM 31 16 Cyton CXP Number of lines to skip before starting the acquisition of lines after the Y windows is opened ...

Page 48: ...SIZE 2 X_SIZE 3 X_SIZE 4 X_SIZE 5 X_SIZE 6 X_SIZE 7 X_SIZE 8 X_SIZE 9 X_SIZE 10 X_SIZE 11 X_SIZE 12 X_SIZE 13 X_SIZE 14 X_SIZE 15 X_SIZE 16 X_OFFS 17 X_OFFS 18 X_OFFS 19 X_OFFS 20 X_OFFS 21 X_OFFS 22 X_OFFS 23 X_OFFS 24 X_OFFS 25 X_OFFS 26 X_OFFS 27 X_OFFS 28 X_OFFS 29 X_OFFS 30 X_OFFS 31 X_OFFS ...

Page 49: ...WIN_DIM 15 0 Cyton CXP Number of 16 byte data words to acquired per line X window This number is only acquired after the X window is opened and after X_OFFS words have been skipped X_OFFS R W X_WIN_DIM 31 16 Cyton CXP Number of 16 byte data words to skip per line after the Z window is opened ...

Page 50: ...V_ACQ_COUNT 7 V_ACQ_COUNT 8 V_ACQ_COUNT 9 V_ACQ_COUNT 10 V_ACQ_COUNT 11 V_ACQ_COUNT 12 V_ACQ_COUNT 13 V_ACQ_COUNT 14 V_ACQ_COUNT 15 V_ACQ_COUNT 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 V_ACQ_COUNT_CLR_MODE 29 V_ACQ_COUNT_CLR_MODE 30 V_ACQ_COUNT_CLR_MODE 31 Reserved ...

Page 51: ...r when it reaches it maximum value depends on the register V_ACQ_COUNT_CLEAR_MODE This register can be written to 0 by software at any time V_ACQ_COUNT_ CLR_MODE R W V_ACQUIRED 29 28 Cyton CXP Controls how the V_ACQ_COUNT register is cleared V_ACQ_COUNT_CLEAR_MODE Meaning 0 00b Clear count on the start of acquisition 1 01b Clear count on the start of V Window 2 10b Clear count on the start of Z Wi...

Page 52: ...UNT 6 Z_ACQ_COUNT 7 Z_ACQ_COUNT 8 Z_ACQ_COUNT 9 Z_ACQ_COUNT 10 Z_ACQ_COUNT 11 Z_ACQ_COUNT 12 Z_ACQ_COUNT 13 Z_ACQ_COUNT 14 Z_ACQ_COUNT 15 Z_ACQ_COUNT 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Z_ACQ_COUNT_CLR_MODE 29 Z_ACQ_COUNT_CLR_MODE 30 Reserved 31 Reserved ...

Page 53: ... reaches it maximum value depends on the register Z_ ACQ_COUNT_CLEAR_MODE This register can be written to 0 by software at any time Z_ACQ_COUNT_ CLR_MODE R W Z_ACQUIRED 29 28 Cyton CXP Controls how the Z_ACQ_COUNT register is cleared Z_ACQ_COUNT_CLEAR_MODE Meaning 0 00b Clear count on the start of acquisition 1 01b Clear count on the start of V Window 2 10b Clear count on the start of Z Window 3 1...

Page 54: ...UNT 6 Y_ACQ_COUNT 7 Y_ACQ_COUNT 8 Y_ACQ_COUNT 9 Y_ACQ_COUNT 10 Y_ACQ_COUNT 11 Y_ACQ_COUNT 12 Y_ACQ_COUNT 13 Y_ACQ_COUNT 14 Y_ACQ_COUNT 15 Y_ACQ_COUNT 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Y_ACQ_COUNT_CLR_MODE 29 Y_ACQ_COUNT_CLR_MODE 30 Reserved 31 Reserved ...

Page 55: ... reaches it maximum value depends on the register Y_ ACQ_COUNT_CLEAR_MODE This register can be written to 0 by software at any time Y_ACQ_COUNT_ CLR_MODE R W Y_ACQUIRED 29 28 Cyton CXP Controls how the Y_ACQ_COUNT register is cleared Y_ACQ_COUNT_CLEAR_MODE Meaning 0 00b Clear count on the start of acquisition 1 01b Clear count on the start of V Window 2 10b Clear count on the start of Z Window 3 1...

Page 56: ...UNT 6 X_ACQ_COUNT 7 X_ACQ_COUNT 8 X_ACQ_COUNT 9 X_ACQ_COUNT 10 X_ACQ_COUNT 11 X_ACQ_COUNT 12 X_ACQ_COUNT 13 X_ACQ_COUNT 14 X_ACQ_COUNT 15 X_ACQ_COUNT 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 X_ACQ_COUNT_CLR_MODE 29 X_ACQ_COUNT_CLR_MODE 30 Reserved 31 Reserved ...

Page 57: ...n it reaches it maximum value depends on the register X_ACQ_COUNT_CLEAR_MODE This register can be written to 0 by software at any time X_ACQ_COUNT_ CLR_MODE R W X_ACQUIRED 29 28 Cyton CXP Controls how the X_ACQ_COUNT register is cleared X_ACQ_COUNT_CLEAR_MODE Meaning 0 00b Clear count on the start of acquisition 1 01b Clear count on the start of V Window 2 10b Clear count on the start of Z Window ...

Page 58: ...T_ENC_A 6 INT_TRIG 7 Reserved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 INT_BM_ERROR 27 INT_AE_LOSS_OF_SYNC 28 INT_PCIE_PKT_DROPPED 29 INT_Z_ACQUIRED_LEGACY 30 Reserved 31 Reserved ...

Page 59: ...rrupt INT_ENC_B R W CON489 4 Cyton CXP Encoder B interrupt INT_ENC_A R W CON489 5 Cyton CXP Encoder A interrupt INT_TRIG R W CON489 6 Cyton CXP Trigger interrupt INT_BM_ERROR R W CON489 26 Cyton CXP Buffer manager interrupt INT_AE_LOSS_ OF_SYNC R W CON489 27 Cyton CXP Loss of sync in the Acquisition Engine interrupt INT_PCIE_PKT_ DROPPED R W CON489 28 Cyton CXP PCIe packet dropped interrupt INT_Z_...

Page 60: ...served 5 Reserved 6 Reserved 7 INT_ANY 8 ENINT_ALL 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 61: ...ync Acquisition Engine CON490 Version A 0 BitFlow Inc CYT 2 39 INT_ANY RO CON490 7 Cyton CXP There is at least on active interrupt on the board ENINT_ALL R W CON490 8 Cyton CXP Set to 1 to enable board interrupts ...

Page 62: ...ENC_A_M 6 INT_TRIG_M 7 Reserved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 INT_BM_ERROR_M 27 INT_AE_LOSS_OF_SYNC_M 28 INT_PCIE_PKT_DROPPED_M 29 INT_Z_ACQUIRED_LEGACY_M 30 Reserved 31 Reserved ...

Page 63: ..._ACQUIRED mask INT_ENC_B_M R W CON548 4 Cyton CXP INT_ENC_B mask INT_ENC_A_M R W CON548 5 Cyton CXP INT_ENC_A mask INT_TRIG_M R W CON548 6 Cyton CXP INT_TRIG mask INT_BM_ ERROR_M R W CON548 26 Cyton CXP INT_BM_ERROR mask INT_AE_LOSS_ OF_SYNC_M R W CON548 27 Cyton CXP INT_AE_LOSS_OF_SYNC mask INT_PCIE_PKT_ DROPPED_M R W CON548 28 Cyton CXP INT_PCIE_PKT_DROPPED mask INT_Z_ ACQUIRED_ LEGACY_M R W CON...

Page 64: ...NC_A_WP 6 INT_TRIG_WP 7 Reserved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 INT_BM_ERROR_WP 27 INT_AE_LOSS_OF_SYNC_WP 28 INT_PCIE_PKT_DROPPED_WP 29 INT_Z_ACQUIRED_LEGACY_WP 30 Reserved 31 Reserved ...

Page 65: ...NC_B_WP R W CON549 4 Cyton CXP INT_ENC_B write protect INT_ENC_A_WP R W CON549 5 Cyton CXP INT_ENC_A write protect INT_TRIG_WP R W CON549 6 Cyton CXP INT_TRIG write protect INT_BM_ ERROR_WP R W CON549 26 Cyton CXP INT_BM_ERROR write protect INT_AE_LOSS_ OF_SYNC_WP R W CON549 27 Cyton CXP INT_AE_LOSS_OF_SYNC write protect INT_PCIE_PKT_ DROPPED_WP R W CON549 28 Cyton CXP INT_PCIE_PKT_DROPPED write p...

Page 66: ...GHT 5 SF_HEIGHT 6 SF_HEIGHT 7 SF_HEIGHT 8 SF_HEIGHT 9 SF_HEIGHT 10 SF_HEIGHT 11 SF_HEIGHT 12 SF_HEIGHT 13 SF_HEIGHT 14 SF_HEIGHT 15 SF_HEIGHT 16 SF_WIDTH 17 SF_WIDTH 18 SF_WIDTH 19 SF_WIDTH 20 SF_WIDTH 21 SF_WIDTH 22 SF_WIDTH 23 SF_WIDTH 24 SF_WIDTH 25 SF_WIDTH 26 SF_WIDTH 27 SF_WIDTH 28 SF_WIDTH 29 SF_WIDTH 30 SF_WIDTH 31 SF_WIDTH ...

Page 67: ...Version A 0 BitFlow Inc CYT 2 45 SF_HEIGHT R W SF_DIM 15 0 Cyton CXP The height in lines of the Synthetic Frame internally generated synthetic image SF_WIDTH R W SF_DIM 31 16 Cyton CXP The width of the Synthetic frame Units are 16 byte chunks ...

Page 68: ...DE 6 Reserved 7 SF_LINE_SCAN 8 SF_INIT_BYTE 9 SF_INIT_BYTE 10 SF_INIT_BYTE 11 SF_INIT_BYTE 12 SF_INIT_BYTE 13 SF_INIT_BYTE 14 SF_INIT_BYTE 15 SF_INIT_BYTE 16 SF_X_GAP 17 SF_X_GAP 18 SF_X_GAP 19 SF_X_GAP 20 SF_Y_GAP 21 SF_Y_GAP 22 SF_Y_GAP 23 SF_Y_GAP 24 SF_Z_GAP 25 SF_Z_GAP 26 SF_Z_GAP 27 SF_Z_GAP 28 SF_INC_X 29 SF_INC_Y 30 SF_INC_Z 31 Reserved ...

Page 69: ...SF_MODE R W SF_CON 5 4 Cyton CXP Describe SF_MODE here SF_LINE_SCAN R W SF_CON 7 Cyton CXP Setting SF_LINE_SCAN to one will put the Synthetic Frame generator in line scan mode SF_INIT_BYTE R W SF_CON 15 8 Cyton CXP The value of the first 8 bit pixel in the synthetic frame SF_X_GAP R W SF_CON 19 16 Cyton CXP The number of pixels between lines Units are 16 byte chunks SF_RUN_LEVEL Meaning Command 0 ...

Page 70: ...N 27 24 Cyton CXP The number of frames between volumes SF_INC_X R W SF_CON 28 Cyton CXP The amount to increment the grey scale output value every pixel SF_INC_Y R W SF_CON 29 Cyton CXP The amount to increment the grey scale output value every line SF_INC_Z R W SF_CON 30 Cyton CXP The amount to increment the grey scale output value every frame ...

Page 71: ...StreamSync system is compatible with the previous BitFlow products However digging deeper these new system have a lot more power and flexibility These new features will be described in the following sections The StreamSync system has many improvements over previous systems The main improvements are Efficient support for variable sized images with fast context switches between frames Per frame cont...

Page 72: ... is Running Stopping Aborting or Stopped If the local Buffer Cache fills and the Acquisition Engine is not currently consuming Quads the Buffer Manager simply waits until room becomes available and pauses loading Quads from the remote QTab Likewise the Acquisition Engine is capable of acquir ing frames as long as it is running and has Quad available to work on If no Quad are available it will simp...

Page 73: ..._LO 9 FIRST_QUAD_PTR_LO 10 FIRST_QUAD_PTR_LO 11 FIRST_QUAD_PTR_LO 12 FIRST_QUAD_PTR_LO 13 FIRST_QUAD_PTR_LO 14 FIRST_QUAD_PTR_LO 15 FIRST_QUAD_PTR_LO 16 FIRST_QUAD_PTR_LO 17 FIRST_QUAD_PTR_LO 18 FIRST_QUAD_PTR_LO 19 FIRST_QUAD_PTR_LO 20 FIRST_QUAD_PTR_LO 21 FIRST_QUAD_PTR_LO 22 FIRST_QUAD_PTR_LO 23 FIRST_QUAD_PTR_LO 24 FIRST_QUAD_PTR_LO 25 FIRST_QUAD_PTR_LO 26 FIRST_QUAD_PTR_LO 27 FIRST_QUAD_PTR_L...

Page 74: ...gister The Cyton CXP CYT 3 4 BitFlow Inc Version A 0 FIRST_QUAD_ PTR_LO R W CON28 31 0 Cyton CXP This is the low word of the 64 bit address of the first DMA scatter gather instruction in a chain of instructions ...

Page 75: ..._HI 9 FIRST_QUAD_PTR_HI 10 FIRST_QUAD_PTR_HI 11 FIRST_QUAD_PTR_HI 12 FIRST_QUAD_PTR_HI 13 FIRST_QUAD_PTR_HI 14 FIRST_QUAD_PTR_HI 15 FIRST_QUAD_PTR_HI 16 FIRST_QUAD_PTR_HI 17 FIRST_QUAD_PTR_HI 18 FIRST_QUAD_PTR_HI 19 FIRST_QUAD_PTR_HI 20 FIRST_QUAD_PTR_HI 21 FIRST_QUAD_PTR_HI 22 FIRST_QUAD_PTR_HI 23 FIRST_QUAD_PTR_HI 24 FIRST_QUAD_PTR_HI 25 FIRST_QUAD_PTR_HI 26 FIRST_QUAD_PTR_HI 27 FIRST_QUAD_PTR_H...

Page 76: ...gister The Cyton CXP CYT 3 6 BitFlow Inc Version A 0 FIRST_QUAD_ PTR_HI R W CON29 31 0 Cyton CXP This is the high word of the 64 bit address of the first DMA scatter gather instruction in a chain of instructions ...

Page 77: ... 5 Reserved 6 Reserved 7 Reserved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 CURR_FETCH_SIZE 25 CURR_FETCH_SIZE 26 CURR_FETCH_SIZE 27 CURR_FETCH_SIZE 28 MAX_FETCH_SIZE 29 MAX_FETCH_SIZE 30 MAX_FETCH_SIZE 31 MAX_FETCH_SIZE ...

Page 78: ...these Quads at one time MAX_FETCH_ SIZE RO BUF_MGR_CON 31 28 Cyton CXP This is the maximum number of Quads that can be fetched as a group by the Buffer Manager The value in this register is derived as a function of the maximum PCIe read request size set by PCI enumeration BM_RUN_LEVEL Meaning 0 0000b Idle The Buffer Manager is not moving data 1 0001b Run The Buffer Manger will start to move data 2...

Page 79: ...OUT 6 QUAD_COMPLETE_TIMEOUT 7 QUAD_COMPLETE_TIMEOUT 8 QUAD_COMPLETE_TIMEOUT 9 QUAD_COMPLETE_TIMEOUT 10 QUAD_COMPLETE_TIMEOUT 11 QUAD_COMPLETE_TIMEOUT 12 QUAD_COMPLETE_TIMEOUT 13 QUAD_COMPLETE_TIMEOUT 14 QUAD_COMPLETE_TIMEOUT 15 QUAD_COMPLETE_TIMEOUT 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Res...

Page 80: ...o wait for a Quad completion Units are 4 nanosec onds Writable only when BM_STATE is Idle DISABLE_ TIMEOUT R W BUF_MGR_TIMEOUT 31 Cyton CXP Setting this bit to 1 will disable the Quad completion timeout mechanism The Buffer Manager will wait an infinite amount of time for a Quad completion to return For debug only Writable only when BM_STATE is Idle ...

Page 81: ...CPLD_MODE 5 CPLD_MODE 6 CPLD_MODE 7 CPLD_MODE 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 CPLD_STRAP 13 CPLD_STRAP 14 CPLD_STRAP 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 82: ... 0 Cyton CXP The current value of the on board switch SW1 CPLD_MODE RO BOARD_CONFIG 7 4 Cyton CXP The current value of switch S3 This switch controls the firmware bank that the FPGA boots from CPLD_STRAP RO BOARD_CONFIG 14 12 Cyton CXP The current value of the three on board straps ...

Page 83: ...M_PACKETS_SENT 9 NUM_PACKETS_SENT 10 NUM_PACKETS_SENT 11 NUM_PACKETS_SENT 12 NUM_PACKETS_SENT 13 NUM_PACKETS_SENT 14 NUM_PACKETS_SENT 15 NUM_PACKETS_SENT 16 NUM_PACKETS_DROP 17 NUM_PACKETS_DROP 18 NUM_PACKETS_DROP 19 NUM_PACKETS_DROP 20 NUM_PACKETS_DROP 21 NUM_PACKETS_DROP 22 NUM_PACKETS_DROP 23 NUM_PACKETS_DROP 24 NUM_PACKETS_DROP 25 NUM_PACKETS_DROP 26 NUM_PACKETS_DROP 27 NUM_PACKETS_DROP 28 NUM...

Page 84: ...gister rolls over to 0 at 0xffff NUM_PACKETS_ DROP RO PACKETS_SENT_STATUS 31 16 Cyton CXP This register indicates the number of PCIe packets that the buffer Manager was not able to send across the PCIe bus because the PCIe bus was busy These packets are dropped but the corresponding Quads are also consumed This means that the Buf fer Manager still stays synchronized and any subsequent packets will...

Page 85: ...S_USED 5 NUM_QUADS_USED 6 NUM_QUADS_USED 7 NUM_QUADS_USED 8 NUM_QUADS_USED 9 NUM_QUADS_USED 10 NUM_QUADS_USED 11 NUM_QUADS_USED 12 NUM_QUADS_USED 13 NUM_QUADS_USED 14 NUM_QUADS_USED 15 NUM_QUADS_USED 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 86: ...Cyton CXP CYT 3 16 BitFlow Inc Version A 0 NUM_QUADS_ USED RO QUADS_USED_STATUS 15 0 Cyton CXP This register indicates the number of Quads that have been consumed by the Buffer Manager This register rolls over to 0 at 0xffff ...

Page 87: ...BS_USED 5 NUM_QTABS_USED 6 NUM_QTABS_USED 7 NUM_QTABS_USED 8 NUM_QTABS_USED 9 NUM_QTABS_USED 10 NUM_QTABS_USED 11 NUM_QTABS_USED 12 NUM_QTABS_USED 13 NUM_QTABS_USED 14 NUM_QTABS_USED 15 NUM_QTABS_USED 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 88: ...Cyton CXP CYT 3 18 BitFlow Inc Version A 0 NUM_QTABS_ USED RO QTABS_USED_STATUS 15 0 Cyton CXP This register indicates the number of QTabs that have been consumed by the Buffer Manager This register rolls over to 0 at 0xffff ...

Page 89: ...5 Reserved 6 Reserved 7 Reserved 8 NO_QUAD_AVAIL 9 VIDEO_DROPPED 10 QUAD_DROPPED 11 Reserved 12 NEW_FRAME_RESYNC 13 RD_ON_EMPTY 14 WR_ON_FULL 15 Reserved 16 PKT_FLUSH_ENABLE 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 90: ... as video from acquisition engine is dropped in order to resynchronize QUAD_ DROPPED RO PKT_STAT 10 Cyton CXP Similar to VIDEO_DROPPED but indicates quad was dropped during re sync process when PKT_STATE equals PKT_SYNC NEW_FRAME_ RESYNC RO PKT_STAT 12 Cyton CXP Reserved RD_ON_EMPTY RO PKT_STAT 13 Cyton CXP FIFO underflow in PacketEngine WR_ON_FULL R W PKT_STAT 14 Cyton CXP FIFO overflow in Packet...

Page 91: ...DMA tries to send as large as packets as possible for efficiency Data is collected in a FIFO until certain size rules are met However sometimes no more data will be com ing end of frame In this case a timeout forces the PacketEngine to transmit the remaining data PKT_FLUSH_ENABLE 1 indicates that this has taken place ...

Page 92: ...M_QUADS_LOADED 6 NUM_QUADS_LOADED 7 NUM_QUADS_LOADED 8 NUM_QUADS_LOADED 9 NUM_QUADS_LOADED 10 NUM_QUADS_LOADED 11 NUM_QUADS_LOADED 12 NUM_QUADS_LOADED 13 NUM_QUADS_LOADED 14 NUM_QUADS_LOADED 15 NUM_QUADS_LOADED 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserv...

Page 93: ...S_LOADED_STATUS Version A 0 BitFlow Inc CYT 3 23 NUM_QUADS_ LOADED RO QUADS_LOADED_STATUS 15 0 Cyton CXP This register indicates the number of Quads that have been loaded by the Buffer Manager This register will roll over to 0 at 0xffff ...

Page 94: ...M_QTABS_LOADED 6 NUM_QTABS_LOADED 7 NUM_QTABS_LOADED 8 NUM_QTABS_LOADED 9 NUM_QTABS_LOADED 10 NUM_QTABS_LOADED 11 NUM_QTABS_LOADED 12 NUM_QTABS_LOADED 13 NUM_QTABS_LOADED 14 NUM_QTABS_LOADED 15 NUM_QTABS_LOADED 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserv...

Page 95: ..._LOADED_STATUS Version A 0 BitFlow Inc CYT 3 25 NUM_QTABS_ LOADED RO QTABS_LOADED_STATUS 15 0 Cyton CXP This register indicates the number of QTabs that have been loaded by the Buffer Man ager This register will roll over to 0 at 0xffff ...

Page 96: ..._CACHED 9 BM_QUADS_CACHED 10 BM_QUADS_CACHED 11 BM_QUADS_CACHED 12 BM_QUADS_CACHED 13 BM_QUADS_CACHED 14 BM_QUADS_CACHED 15 BM_QUADS_CACHED 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 DST_ADDR_ERROR_LSB 21 NEXT_ADDR_ERROR_LSB 22 SIZE_ERROR_LSB 23 SIZE_ERROR_MSB 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 CPL_ERROR 29 QUAD_NUM_MISMATCH 30 QUAD_FIFO_OVERFLOW 31 QUAD_TIMEOUT_DETECTED ...

Page 97: ...LSB RO BUF_MGR_STATUS 20 Cyton CXP Quad destination address is not 16 byte aligned NEXT_ADDR_ ERROR_LSB RO BUF_MGR_STATUS 21 Cyton CXP Quad points to a next quad that is not 16 byte aligned SIZE_ERROR_ LSB RO BUF_MGR_STATUS 22 Cyton CXP Quad size is not a multiple of 16 bytes SIZE_ERROR_ MSB RO BUF_MGR_STATUS 23 Cyton CXP Quad size is 4K BM_STATE Meaning 0 0000b Idle The buffer manager is not curr...

Page 98: ...ad Check CPL_STATUS QUAD_NUM_ MISMATCH RO BUF_MGR_STATUS 29 Cyton CXP Actual quad number does not match expected QUAD_FIFO_ OVERFLOW RO BUF_MGR_STATUS 30 Cyton CXP Quad cache overflowed QUAD_ TIMEOUT_ DETECTED RO BUF_MGR_STATUS 31 Cyton CXP Timeout waiting for a Quad completion A different timeout value can be set in the QUAD_COMPLETE_TIMEOUT register ...

Page 99: ...PAYLOAD_PCIE 5 MAX_PAYLOAD_PCIE 6 MAX_PAYLOAD_PCIE 7 MAX_PAYLOAD_PCIE 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 DISABLE_PKT_FLUSH_TIMER 31 DISABLE_PKT_GEN ...

Page 100: ... testing purposes only MAX_PAYLOAD_PCIE is status only and does not control internal logic MAX_PAYLOAD_USER does control internal logic DISABLE_PKT_ FLUSH_TIMER R W PKT_CON 30 Cyton CXP Deactivate the timer that flushes video data to PCIe when the FIFO is inactive for an extended period Note This bit is for degging purposes only DISABLE_PKT_ GEN R W PKT_CON 31 Cyton CXP Disable the generation of o...

Page 101: ...iggering at arbitrary points in a pulse train 4 1 1 Description TS Table The TS is programmed through the TS registers The sequence of pulse that the TS will put out is programmed by building up instructions in the TS table The table can hold up to 256 instructions which can create extremely complex signals The TS Table is programmed indirectly via address data type registers Once the table is pro...

Page 102: ...e either high or low 0 or 1 By programming both high pulses and low pulses any pulse train can be created Chaining Pulses Pulses are chained together link a linked list Each pulse entry have a next field which tells the system where in the table the next pulse should come from This facility is used to build up complex sequences as well as looping sequences Triggering Each entry in the TS table can...

Page 103: ...1_DEFAULT_STATE 6 TS_CT2_DEFAULT_STATE 7 TS_CT3_DEFAULT_STATE 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 TS_IDX_JUMP 17 TS_IDX_JUMP 18 TS_IDX_JUMP 19 TS_IDX_JUMP 20 TS_IDX_JUMP 21 TS_IDX_JUMP 22 TS_IDX_JUMP 23 TS_IDX_JUMP 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 104: ...le TS_CT1_ DEFAULT_STATE R W TS_CONTROL 5 Cyton CXP This is the output state of CT1 when the TS is Idle TS_CT2_ DEFAULT_STATE R W TS_CONTROL 6 Cyton CXP This is the output state of CT2 when the TS is Idle TS_CT3_ DEFAULT_STATE R W TS_CONTROL 7 Cyton CXP This is the output state of CT3 when the TS is Idle TS_IDX_JUMP R W TS_CONTROL 23 16 Cyton CXP This is the entry that the table will start from wh...

Page 105: ...Timing Sequencer TS_CONTROL Version A 0 BitFlow Inc CYT 4 5 This is the entry that the table sill jump to synchronously the TS_RUN_LEVEL register is set to Jump ...

Page 106: ...CESS 4 TS_IDX_ACCESS 5 TS_IDX_ACCESS 6 TS_IDX_ACCESS 7 TS_IDX_ACCESS 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 107: ...ng Sequencer TS_TABLE_CONTROL Version A 0 BitFlow Inc CYT 4 7 TS_IDX_ACCESS R W TS_TABLE_CONTROL 7 0 Cyton CXP Table index to access Address is setup here Access is done through read write to TS_TABLE_ENTRY ...

Page 108: ...S_NEXT 7 TS_NEXT 8 Reserved 9 Reserved 10 TS_RESOLUTION 11 TS_RESOLUTION 12 TS_STATE_CT0 13 TS_STATE_CT1 14 TS_STATE_CT2 15 TS_STATE_CT3 16 Reserved 17 TS_COUNT 18 TS_COUNT 19 TS_COUNT 20 TS_COUNT 21 TS_COUNT 22 TS_COUNT 23 TS_COUNT 24 TS_COUNT 25 TS_COUNT 26 TS_COUNT 27 TS_CONDITION 28 TS_CONDITION 29 TS_CONDITION 30 TS_TERMINATE 31 TS_END_OF_SEQUENCE ...

Page 109: ...NTRY 12 Cyton CXP The level of the CT0 signal for this pulse TS_STATE_CT1 R W TS_TABLE_ENTRY 13 Cyton CXP The level of the CT1 signal for this pulse TS_STATE_CT2 R W TS_TABLE_ENTRY 14 Cyton CXP The level of the CT2 signal for this pulse TS_STATE_CT3 R W TS_TABLE_ENTRY 15 Cyton CXP The level of the CT3 signal for this pulse TS_COUNT R W TS_TABLE_ENTRY 26 17 Cyton CXP The length of this pulse The un...

Page 110: ...S_NEXT bitfield after the current pulse is finished TS_END_OF_ SEQUENCE R W TS_TABLE_ENTRY 31 Cyton CXP If this bit is set to 1 and TS_RUN_LEVEL is set to Jump the TS will jump to the index set in the TS_INDX_JUMP bitfield after the current pulse is output This bit allows for syn chronous switching between one section of the table and another section If thte TS_RUN_LEVEL bitfield is not set to Jum...

Page 111: ...ward only stage movements The system can be be programmed to only acquire one line for each encoder count that corresponds to a physical location on the stage The encoder counter can be used in many different ways described in more details below 5 1 1 Simple Encoder Mode The most basic method of using a quadrature encoder is to use it like a standard sig nal phase encoder In this mode the quadratu...

Page 112: ...ty of the mechanical system vibrating jumping bouncing etc If these imperfections occur during the period of time where lines are being acquired the image will be distorted Lines on the object can be acquired more than once as the stage jitters To prevent re acquisition of lines a circuit has been added to the quadrature encoder system that can prevent any line from being acquired more than once T...

Page 113: ...r that you wish to connect to For example if you want to connect a TLL A output to VFG 0 then you would use VFG0_ENCODER_TTL Table 5 1 Observability Registers Register Meaning QENC_COUNT Encoder counter QENC_PHASEA Phase of input A QENC_PHASEB Phase of input B QENC_DIR Direction of encoder QENC_INTRVL_IN Interval status QENC_NEW_LINES Indicates new lines are being acquired Table 5 2 TTL Quadrature...

Page 114: ...ncoder could be attached to any mechanical system however a back and forth stage is a simple way to illustrate these modes In Figure 5 1 you can see as the stage moves back and forth the encoder counts up and down Further in this example we assume QENC_AQ_DIR 1 which tells the sys tem to only acquire when the encoder counter is moving in the positive direction This is illustrated by solid lines in...

Page 115: ...ure Encoder Modes Version A 0 BitFlow Inc CYT 5 5 Figure 5 2 shows all of the major quadrature encoder modes Figure 5 2 Quadrature Encoder Modes vs Acquisition Positive Negative Both Acquisition Direction Simple No Re Acquire Interval Not Valid Zoom In Mode ...

Page 116: ...L_LL 8 QENC_INTRVL_LL 9 QENC_INTRVL_LL 10 QENC_INTRVL_LL 11 QENC_INTRVL_LL 12 QENC_INTRVL_LL 13 QENC_INTRVL_LL 14 QENC_INTRVL_LL 15 QENC_INTRVL_LL 16 QENC_INTRVL_LL 17 QENC_INTRVL_LL 18 QENC_INTRVL_LL 19 QENC_INTRVL_LL 20 QENC_INTRVL_LL 21 QENC_INTRVL_LL 22 QENC_INTRVL_LL 23 QENC_INTRVL_LL 24 QENC_DECODE 25 QENC_AQ_DIR 26 QENC_AQ_DIR 27 QENC_INTRVL_MODE 28 QENC_NO_REAQ 29 QENC_DUAL_PHASE 30 SCAN_S...

Page 117: ...red Whether lines are acquired as the counter incre ments through the interval or decrements through the interval or in both directions are controlled by QENC_AQ_DIR QENC_NO_ REAQ R W CON15 28 Karbon Neon This bit controls how the quadrature encoder system handles the situation where the encoder does not smoothly increase or decrease if QENC_AQ_DIR 1 If there is jitter in the encoder signal often ...

Page 118: ...ugh a value or to what extremes the counter goes New lines will only be acquired when new values are reached Once the entire frame has been acquired the system must be reset The system can always be reset by poking QENC_RESET to 1 There are also ways that the system can automatically be reset see QENC_RESET_MODE QENC_DUAL_ PHASE R W CON15 29 Karbon Neon This bit controls which type of encoder is a...

Page 119: ...Quadrature Encoder CON15 Register Version A 0 BitFlow Inc CYT 5 9 QENC_RESET WO CON15 31 Karbon Neon Poking this bit to a 1 resets the entire quadrate encoder system ...

Page 120: ...NTRVL_UL 7 QENC_INTRVL_UL 8 QENC_INTRVL_UL 9 QENC_INTRVL_UL 10 QENC_INTRVL_UL 11 QENC_INTRVL_UL 12 QENC_INTRVL_UL 13 QENC_INTRVL_UL 14 QENC_INTRVL_UL 15 QENC_INTRVL_UL 16 QENC_INTRVL_UL 17 QENC_INTRVL_UL 18 QENC_INTRVL_UL 19 QENC_INTRVL_UL 20 QENC_INTRVL_UL 21 QENC_INTRVL_UL 22 QENC_INTRVL_UL 23 QENC_INTRVL_UL 24 QENC_REAQ_MODE 25 QENC_REAQ_MODE 26 QENC_RESET_REAQ 27 N A 28 N A 29 N A 30 N A 31 N ...

Page 121: ...ic modes do not require host interaction the reset will occur automatically when the specified conditions are met QENC_RESET_ REAQ WO CON16 26 Karbon Neon This register is used to reset the circuit that prevents the re acquisition of lines when QENC_NO_REAQ is set to 1 Writing a 1 to this register deletes the list of acquired lines thus next time the lines are passed over they will be acquired aga...

Page 122: ...erved 5 Reserved 6 Reserved 7 Reserved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 SCAN_STEP 17 SCAN_STEP 18 SCAN_STEP 19 SCAN_STEP 20 SCAN_STEP 21 SCAN_STEP 22 SCAN_STEP 23 SCAN_STEP 24 SCAN_STEP 25 SCAN_STEP 26 SCAN_STEP 27 SCAN_STEP 28 SCAN_STEP 29 SCAN_STEP 30 SCAN_STEP 31 SCAN_STEP ...

Page 123: ...CAN_STEP R WO CON22 31 16 Karbon Neon This bitfield controls the number of encoder pulses that must occur before a trigger is issued to the system See SCAN_STEP_TRIG for more information The Scan Step cir cuit takes into account the interval and re acquisition functions ...

Page 124: ...UNT 6 QENC_COUNT 7 QENC_COUNT 8 QENC_COUNT 9 QENC_COUNT 10 QENC_COUNT 11 QENC_COUNT 12 QENC_COUNT 13 QENC_COUNT 14 QENC_COUNT 15 QENC_COUNT 16 QENC_COUNT 17 QENC_COUNT 18 QENC_COUNT 19 QENC_COUNT 20 QENC_COUNT 21 QENC_COUNT 22 QENC_COUNT 23 QENC_COUNT 24 QENC_PHASEA 25 QENC_PHASEB 26 QENC_DIR 27 QENC_INTRVL_IN 28 QENC_NEW_LINES 29 Reserved 30 Reserved 31 Reserved ...

Page 125: ... QENC_DIR RO CON51 26 Karbon Neon This bit displays the current quadrature encoder direction QENC_INTRVL_ IN RO CON51 27 Karbon Neon This bit indicates the current status of the quadrature encoder if the system is in inter val mode see QENC_INTRVL_MODE QENC_DIR Meaning 0 Direction is negative 1 Direction is positive QENC_INTRVL_IN Meaning 0 System is not inside the interval Encoder counter is not ...

Page 126: ...n QENC_NO_REAQ 1 only lines that have not yet been scanned are acquired This bit can be used to determine of new lines are being traversed or if the system has backed up and is revisiting old lines QENC_NEW_LINES Meaning 0 The system is traversing lines that have already been visited If QENC_NO_REAQ 1 lines are not being acquired 1 The system is traversing new lines Lines are being acquired ...

Page 127: ...3448 or 4 2666 Of course not all ration numbers in the available scaling range can be selected there are an infinite number of them However a useful selection of values is available which should support most applications The Encoder Divider circuit takes as its input the selected encoder input controlled by the register SELENC The output of the encoder divider drives the same parts of the board th...

Page 128: ...two extremes and the scaling factors are not evenly distributed However a scaling factor can be generally found that meets the requirments of most applications 6 2 2 Example Let s assume that the encoder frequency Fin is 10 KHz and that we need an output Fout of 30 KHz This means that we need to multiply by 3 Set N 6 and M 21 This will a scaling factor of 3 048 The result is an effective line rate...

Page 129: ... avoid this situation and handle encoder slow down stop gracefully the encoder divider has has limiting cir cuit that can be run in one of two different mode described in the following two sec tions Slow Tracking Mode ENC_DIC_FORCE_DC 0 In this mode when the input frequency goes below the minimum of 1 6 KHz the Encoder Divider circuit s output will continue to track the input but the output fre qu...

Page 130: ...ntrols the N factor the Encoder Divider equation ENC_DIV_FORCE_DC CON16 27 Controls the behavior when Fin falls below the minimum 0 Output runs in simple divider mode 1 Output goes to DC ENC_DIV_OPEN_LOOP CON16 28 Controls whether the output signal phase of the Encoder Divider is lock to the intput or is allowed to free run 0 Output phased locked to input 1 Ouput runs open loop ENC_DIV_FCLK_SEL CO...

Page 131: ...egisters Introduction Version A 0 BitFlow Inc CYT 7 1 Karbon Cyton CXP I O System Registers Chapter 7 7 1 Introduction The registers documented in this section are used to control the I O system on the Karbon CXP and the Cyton CXP ...

Page 132: ..._IN_TTL 7 RD_BOX_IN_TTL 8 RD_BOX_IN_TTL 9 RD_BOX_IN_TTL 10 RD_BOX_IN_TTL 11 Reserved 12 RD_BOX_IN_DIF 13 RD_BOX_IN_DIF 14 RD_BOX_IN_DIF 15 RD_BOX_IN_DIF 16 RD_BOX_IN_DIF 17 RD_BOX_IN_DIF 18 RD_BOX_IN_DIF 19 RD_BOX_IN_DIF 20 RD_BOX_IN_DIF 21 RD_BOX_IN_DIF 22 RD_BOX_IN_DIF 23 Reserved 24 ENINT_CXP 25 INT_CXP 26 Reserved 27 Reserved 28 Reserved 29 SW_TRIG 30 SW_ENCA 31 SW_ENCB ...

Page 133: ...icates the existence of an interrupt from the CXP subsystem The individual interrupt must be cleared in the CXP subsystem in order for this bit to reset SW_TRIG R W CON60 29 Karbon CXP Cyton CXP Writing the bit to 1 causes the internal trigger signal to be asserted Writing it to a 0 will de assert the internal trigger signal SW_ENCA R W CON60 30 Karbon CXP Cyton CXP Writing the bit to 1 causes the...

Page 134: ...BOX_IN_OPTO 7 RD_BOX_IN_OPTO 8 RD_BOX_IN_OPTO 9 RD_BOX_IN_OPTO 10 RD_BOX_IN_OPTO 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 RD_CXP_TRIG_OUT 24 RD_CXP_OUT_IN 25 RD_CXP_OUT_IN 26 RD_CXP_OUT_IN 27 RD_CXP_OUT_IN 28 RD_CXP_OUT_IN 29 RD_CXP_OUT_IN 30 RD_CXP_OUT_IN 31 RD_CXP_OUT_IN ...

Page 135: ...eal time state of the 12 Opto Isolated inputs on the IO Box RD_CXP_TRIG_ OUT RO CON61 23 Karbon CXP Cyton CXP This bit reflects the real time state of the CXP trigger signal going to the camera RD_CXP_IO_ OUT RO CON61 31 24 Karbon CXP Cyton CXP These bits reflects the real time state of board s 8 CXP general purpose output signals going to the camera ...

Page 136: ... RD_ENCA_VFG0 8 RD_ENCA_SW 9 RD_ENCB_TTL 10 RD_ENCB_DIF 11 RD_ENCB_VFG0 12 RD_ENCB_SW 13 RD_BUTTON 14 Reserved 15 Reserved 16 RD_CXP_IO_IN 17 RD_CXP_IO_IN 18 RD_CXP_IO_IN 19 RD_CXP_IO_IN 20 RD_CXP_IO_IN 21 RD_CXP_IO_IN 22 RD_CXP_IO_IN 23 RD_CXP_IO_IN 24 RD_CXP_TRIG_IN 25 EN_TRIG 26 EN_ENCA 27 EN_ENCB 28 Reserved 29 RD_ENCB_SELECTED 30 RD_ENCA_SELECTED 31 RD_TRIG_SELECTED ...

Page 137: ... output from the quadrature encoder circuit RD_SW_TRIG RO CON62 4 Karbon CXP Cyton CXP This bit reflects the real time state of the board s software trigger RD_ENCA_TTL RO CON62 5 Karbon CXP Cyton CXP This bit reflects the real time state of the board s TTL encoder A input RD_ENCA_DIF RO CON62 6 Karbon CXP Cyton CXP This bit reflects the real time state of the board s differential encoder A input ...

Page 138: ...s button input RD_CXP_IO_IN RO CON62 23 16 Karbon CXP Cyton CXP These bits reflects the real time state of board s 8 CXP general purpose input signals coming from the camera RD_CXP_TRIG_ IN RO CON62 24 Karbon CXP Cyton CXP This bit reflects the real time state of the CXP trigger signal coming from the camera EN_TRIG R W CON62 25 Karbon CXP Cyton CXP This bit is used to enable the selected trigger ...

Page 139: ...nc CYT 7 9 RD_ENCA_ SELECTED RO CON62 30 Karbon CXP Cyton CXP The bit reflects the real time status of the board s selected encoder A input RD_TRIG_ SELECTED RO CON62 31 Karbon CXP Cyton CXP The bit reflects the real time status of the board s selected trigger input ...

Page 140: ...4 SEL_TRIG 5 SEL_TRIG 6 SEL_ENCA 7 SEL_ENCA 8 SEL_ENCA 9 SEL_ENCA 10 SEL_ENCA 11 SEL_ENCA 12 SEL_ENCB 13 SEL_ENCB 14 SEL_ENCB 15 SEL_ENCB 16 SEL_ENCB 17 SEL_ENCB 18 SEL_CC1 19 SEL_CC1 20 SEL_CC1 21 SEL_CC1 22 SEL_CC2 23 SEL_CC2 24 SEL_CC2 25 SEL_CC2 26 Reserved 27 Reserved 28 SEL_LED 29 SEL_LED 30 SEL_LED 31 SEL_LED ...

Page 141: ...110b Button 7 000111b The camera s CXP trigger VFGx_CXP_TRIG 8 001000b This VFG s software trigger SW_TRIG 9 001001b This VFG s scan step circuit 10 001010b VFG0 s NTG or TS VFG0_NTG or VFG0_TS 11 27 Reserved 28 to 39 BOX_IN_TTL_0 to BOX_IN_TTL_11 40 to 51 BOX_IN_DIF_0 to BOX_IN_DIF_11 52 to 63 BOS_IN_OPT_0 to BOX_IN_OPT_11 SEL_ENCA Source 0 000000b Forced low 1 000001b Forced high 2 000010b This ...

Page 142: ...e 0 000000b Forced low 1 000001b Forced high 2 000010b This VFG s differential encoder B VFGx_ENCB 3 000011b This VFG s TTL encoder B VFGx_ENCB_TTL 4 000100b Selected encoder B from VFG0 VFG0_ENCB_SEL 5 000101b This VFG s NTG or TS VFGx_NTG VFGx_TS 6 000110b Button 7 000111b The camera s CXP trigger VFGx_CXP_TRIG 8 001000b This VFG s software encoder B SW_ENCB 9 001001b VFG0 s NTG or TS VFG0_NTG o...

Page 143: ...or TS 5 0101b CT3 from CTabs or TS 6 0110b VFGx_TRIG_SEL 7 0111b VFGx_ENCA_SEL 8 1000b VFGx_ENCB_SEL 9 1001b This VFG s NTG or TS VFGx_NTG or VFGx_TS 10 1010b VFG0 s NTG or TS VFG0_NTG or VFG0_TS 11 15 Reserved SEL_CC1 Source 0 0000b Forced low 1 0001b Forced high 2 0010b CT0 from CTabs or TS 3 0011b CT1 from CTabs or TS 4 0100b CT2 from CTabs or TS 5 0101b CT3 from CTabs or TS 6 0110b VFGx_TRIG_S...

Page 144: ...ry time the selected event asserts SEL_CC1 Source 0 0000b Board emits an interrupt to the host 1 0001b VFGx_TRIG_SEL 2 0010b VFG0_TRIG_SEL 3 0011b Button 4 0100b FVAL from camera 5 0101b VAW 6 0110b VWIN 7 0111b CC1 8 1000b CC2 9 1001b CC3 10 1010b CC4 11 1011b VFGx_NTG or VFGx_TS 12 1100b VFG0_NTG or VFG0_TS 13 1101b AQSTAT 1 14 1110b Overstep OVS 15 1111b Reserved ...

Page 145: ...L_CC3 4 SEL_CC4 5 SEL_CC4 6 SEL_CC4 7 SEL_CC4 8 SEL_BOX_OUT_TTL 9 SEL_BOX_OUT_DIF 10 SEL_BOX_OUT_OPTO 11 Reserved 12 Reserved 13 TRIGPOL 14 ENCA_POL 15 ENCB_POL 16 GPOUT0 17 GPOUT1 18 GPOUT2 19 GPOUT3 20 GPOUT4 21 GPOUT5 22 GPOUT6 23 GPOUT7 24 GPOUT8 25 GPOUT9 26 GPOUT10 27 GPOUT11 28 LED_RED 29 LED_ORANGE 30 LED_GREEN 31 Reserved ...

Page 146: ...CT3 from CTabs or TS 6 0110b VFGx_TRIG_SEL 7 0111b VFGx_ENCA_SEL 8 1000b VFGx_ENCB_SEL 9 1001b This VFG s NTG or TS VFGx_NTG or VFGx_TS 10 1010b VFG0 s NTG or TS VFG0_NTG or VFG0_TS 11 15 Reserved SEL_CC4 Source 0 0000b Forced low 1 0001b Forced high 2 0010b CT0 from CTabs or TS 3 0011b CT1 from CTabs or TS 4 0100b CT2 from CTabs or TS 5 0101b CT3 from CTabs or TS 6 0110b VFGx_TRIG_SEL 7 0111b VFG...

Page 147: ... W CON64 13 Karbon CXP Cyton CXP Selects the edge of the trigger signal the corresponds to its assertion SEL_BOX_OUT_TTL Meaning 0 IOBOX TTL outputs are driven GPOUT0 to GPOUT11 1 IOBOX TTL outputs are driven by VFG0_CC1 to VFG3_CC3 SEL_BOX_OUT_DIF Meaning 0 IOBOX differential outputs are driven GPOUT0 to GPOUT11 1 IOBOX differential outputs are driven by VFG0_CC1 to VFG3_CC3 SEL_BOX_OUT_DIF Meani...

Page 148: ...tput bit 0 GPOUT1 R W CON64 17 Karbon CXP Cyton CXP General purpose output bit 1 GPOUT2 R W CON64 18 Karbon CXP Cyton CXP General purpose output bit 2 GPOUT3 R W CON64 19 Karbon CXP Cyton CXP General purpose output bit 3 GPOUT4 R W CON64 20 Karbon CXP Cyton CXP General purpose output bit 4 GPOUT5 R W CON64 21 Karbon CXP Cyton CXP General purpose output bit 5 ENCA_POL Meaning 0 Encoder A asserted o...

Page 149: ...it 8 GPOUT9 R W CON64 25 Karbon CXP Cyton CXP General purpose output bit 9 GPOUT10 R W CON64 26 Karbon CXP Cyton CXP General purpose output bit 10 GPOUT11 R W CON64 27 Karbon CXP Cyton CXP General purpose output bit 11 LED_RED R W CON64 28 Karbon CXP Cyton CXP Setting this bit to 1 turns the red LED on LED_ORANGE R W CON64 29 Karbon CXP Cyton CXP Setting this bit to 1 turns the orange LED on LED_G...

Page 150: ...CON64 The Cyton CXP CYT 7 20 BitFlow Inc Version A 0 ...

Page 151: ...ingle dual or quad link One VFG typi cally controls one camera so each VFG needs access to all the links that belong to the connected camera To illustrate this concept lets look at the Karbon CXP4 This has 4 CXP links and 4 VFGs There are quite a few ways that the cameras can be connected to VFGs This board could be connected to four single link camera in which case each VFG gets date from one CXP...

Page 152: ..._UNDER_LATCH 10 0_POCXP_24V_OK 11 Reserved 12 0_POCXP_STATE 13 0_POCXP_OVR_AUTO_RESTART 14 0_POCXP_SENSE_BYPASS 15 0_ENABLE_POCXP_SYSTEM 16 0_POCXP_CURRENT_LATCH 17 0_POCXP_CURRENT_LATCH 18 0_POCXP_CURRENT_LATCH 19 0_POCXP_CURRENT_LATCH 20 0_POCXP_CURRENT_LATCH 21 0_POCXP_CURRENT_LATCH 22 0_POCXP_CURRENT_LATCH 23 0_POCXP_CURRENT_LATCH 24 0_POCXP_CURRENT 25 0_POCXP_CURRENT 26 0_POCXP_CURRENT 27 0_P...

Page 153: ... the camera in response to POCXP_EN_CAM_SENSE 0_POCXP_ OPEN_ DETECTED RO CON104 5 Karbon CXP Cyton CXP Only valid if POCXP_EN_CAM_SENSE is asserted This status bit tells if an open circuit was detected from the camera in response to POCXP_EN_CAM_SENSE It likely means there is no camera detected 0_POCXP_ OVER_ DETECTED RO CON104 6 Karbon CXP Cyton CXP This status bit indicated over current detected...

Page 154: ..._POCXP_ STATE RO CON104 12 Karbon CXP Cyton CXP TBD 0_POCXP_OVR_ AUTO_RESTART RW CON104 13 Karbon CXP Cyton CXP TBD 0_POCXP_ SENSE_BYPASS RW CON104 14 Karbon CXP Cyton CXP TBD 0_ENABLE_ POCXP_SYSTEM RW CON104 15 Karbon CXP Cyton CXP This bit turns on the entire POCXP system If this bit is zero this link will not be pow ered up If this bit is 1 then the link will be powered if there is a POCXP came...

Page 155: ...CXP Subsystem Registers CON104 Version A 0 BitFlow Inc CYT 8 5 0_POCXP_ CURRENT RO CON104 31 24 Karbon CXP Cyton CXP Real time current indicator ...

Page 156: ... 10 0_POCXP_OVER_TIMER 11 0_POCXP_OVER_TIMER 12 0_POCXP_OVER_TIMER 13 0_POCXP_OVER_TIMER 14 0_POCXP_OVER_TIMER 15 0_POCXP_OVER_TIMER 16 0_POCXP_OVER_TIMER 17 0_POCXP_OVER_TIMER 18 0_POCXP_OVER_TIMER 19 0_POCXP_OVER_TIMER 20 0_POCXP_OVER_TIMER 21 0_POCXP_OVER_TIMER 22 0_POCXP_OVER_TIMER 23 0_POCXP_OVER_TIMER 24 0_POCXP_OVER_TIMER 25 0_POCXP_OVER_TIMER 26 0_POCXP_OVER_TIMER 27 0_POCXP_OVER_TIMER 28 ...

Page 157: ...CON105 31 0 Karbon CXP Cyton CXP This register specifies the time in 6 4ns units to wait after both POCXP_EN_POWER and POCXP_EN_24_REG transition from 0 to 1 before enabling the overcurrent detection circuit It should be set high enough to ignore transients that may occur on initial power ...

Page 158: ...POCXP_UNDER_TIMER 11 0_POCXP_UNDER_TIMER 12 0_POCXP_UNDER_TIMER 13 0_POCXP_UNDER_TIMER 14 0_POCXP_UNDER_TIMER 15 0_POCXP_UNDER_TIMER 16 0_POCXP_UNDER_TIMER 17 0_POCXP_UNDER_TIMER 18 0_POCXP_UNDER_TIMER 19 0_POCXP_UNDER_TIMER 20 0_POCXP_UNDER_TIMER 21 0_POCXP_UNDER_TIMER 22 0_POCXP_UNDER_TIMER 23 0_POCXP_UNDER_TIMER 24 0_POCXP_UNDER_TIMER 25 0_POCXP_UNDER_TIMER 26 0_POCXP_UNDER_TIMER 27 0_POCXP_UND...

Page 159: ...ON106 31 0 Karbon CXP Cyton CXP This register specifies the time in 6 4ns units to wait after both POCXP_EN_POWER and POCXP_EN_24_REG transition from 0 to 1 before enabling the under current detection circuit It should be set high enough to ignore transients that may occur on initial power ...

Page 160: ...FIFO_SIZE 11 0_COM_RCV_FIFO_SIZE 12 0_COM_RCV_FIFO_SIZE 13 0_COM_RCV_FIFO_SIZE 14 0_COM_RCV_FIFO_SIZE 15 0_COM_RCV_FIFO_SIZE 16 0_COM_SEND_FIFO_SIZE 17 0_COM_SEND_FIFO_SIZE 18 0_COM_SEND_FIFO_SIZE 19 0_COM_SEND_FIFO_SIZE 20 0_COM_SEND_FIFO_SIZE 21 0_COM_SEND_FIFO_SIZE 22 0_COM_SEND_FIFO_SIZE 23 0_COM_SEND_FIFO_SIZE 24 0_COM_SEND_FIFO_SIZE 25 0_COM_SEND_FIFO_SIZE 26 0_COM_SEND_FIFO_SIZE 27 0_COM_SE...

Page 161: ...1 0_COM_RCV_ FIFO_SIZE RO CON107 15 0 Karbon CXP Cyton CXP Depth of the control channel receive fifo It is measured in 32 bit words 0_COM_SEND_ FIFO_SIZE RO CON107 31 16 Karbon CXP Cyton CXP Depth of the control channel request fifo It is measured in 32 bit words ...

Page 162: ...rved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 0_COM_SEND_FIFO_CNT 17 0_COM_SEND_FIFO_CNT 18 0_COM_SEND_FIFO_CNT 19 0_COM_SEND_FIFO_CNT 20 0_COM_SEND_FIFO_CNT 21 0_COM_SEND_FIFO_CNT 22 0_COM_SEND_FIFO_CNT 23 0_COM_SEND_FIFO_CNT 24 0_COM_SEND_FIFO_CNT 25 0_COM_SEND_FIFO_CNT 26 0_COM_SEND_FIFO_CNT 27 0_COM_SEND_FIFO_CNT 28 0_COM_SEND_FIFO_CNT 29 0_COM_SEND_FIFO_CNT 30 0_COM_SEND_FIFO_CNT 31...

Page 163: ..._ GO WO CON108 1 Karbon CXP Cyton CXP Transmit the packet stored in the request fifo to the uplink channel This involves an 8b 10b encoding and serialization It is assumed that the packet was constructed in the fifo by software and is ready for transmission 0_COM_SEND_ FIFO_CNT RO CON108 31 16 Karbon CXP Cyton CXP Number of 32 bit words currently in the request fifo ...

Page 164: ... 9 0_COM_SEND_DATA 10 0_COM_SEND_DATA 11 0_COM_SEND_DATA 12 0_COM_SEND_DATA 13 0_COM_SEND_DATA 14 0_COM_SEND_DATA 15 0_COM_SEND_DATA 16 0_COM_SEND_DATA 17 0_COM_SEND_DATA 18 0_COM_SEND_DATA 19 0_COM_SEND_DATA 20 0_COM_SEND_DATA 21 0_COM_SEND_DATA 22 0_COM_SEND_DATA 23 0_COM_SEND_DATA 24 0_COM_SEND_DATA 25 0_COM_SEND_DATA 26 0_COM_SEND_DATA 27 0_COM_SEND_DATA 28 0_COM_SEND_DATA 29 0_COM_SEND_DATA 3...

Page 165: ... responsible for constructing the majority of the CXP packed according to the CXP specification Hardware will automatically generate the leading start of packet indication K27 7 the control command indication 0x2 and the trailing end of packet indication K29 7 All other fields cmd size addr data crc are left to software Once the packet is formed software should assert the COM_ SEND_GO bit Reading ...

Page 166: ... Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 0_COM_RCV_FIFO_CNT 17 0_COM_RCV_FIFO_CNT 18 0_COM_RCV_FIFO_CNT 19 0_COM_RCV_FIFO_CNT 20 0_COM_RCV_FIFO_CNT 21 0_COM_RCV_FIFO_CNT 22 0_COM_RCV_FIFO_CNT 23 0_COM_RCV_FIFO_CNT 24 0_COM_RCV_FIFO_CNT 25 0_COM_RCV_FIFO_CNT 26 0_COM_RCV_FIFO_CNT 27 0_COM_RCV_FIFO_CNT 28 0_COM_RCV_FIFO_CNT 29 0_COM_RCV_FIFO_CNT 30 0_COM_RCV_FIFO_CNT 31 0_COM_RCV...

Page 167: ...ersion A 0 BitFlow Inc CYT 8 17 0_COM_RCV_ FIFO_CLR WO CON110 0 Karbon CXP Cyton CXP Clear the control channel receive fifo 0_COM_RCV_ FIFO_CNT RO CON110 31 16 Karbon CXP Cyton CXP Number of 32 bit words currently in the response fifo ...

Page 168: ...CV_DATA 9 0_COM_RCV_DATA 10 0_COM_RCV_DATA 11 0_COM_RCV_DATA 12 0_COM_RCV_DATA 13 0_COM_RCV_DATA 14 0_COM_RCV_DATA 15 0_COM_RCV_DATA 16 0_COM_RCV_DATA 17 0_COM_RCV_DATA 18 0_COM_RCV_DATA 19 0_COM_RCV_DATA 20 0_COM_RCV_DATA 21 0_COM_RCV_DATA 22 0_COM_RCV_DATA 23 0_COM_RCV_DATA 24 0_COM_RCV_DATA 25 0_COM_RCV_DATA 26 0_COM_RCV_DATA 27 0_COM_RCV_DATA 28 0_COM_RCV_DATA 29 0_COM_RCV_DATA 30 0_COM_RCV_DA...

Page 169: ...system Registers CON111 Version A 0 BitFlow Inc CYT 8 19 0_COM_RCV_ DATA RO CON111 31 0 Karbon CXP Cyton CXP Read the head of the control channel response fifo Fifo level can be monitored with COM_RCV_FIFO_CNT ...

Page 170: ...ed 4 Reserved 5 Reserved 6 Reserved 7 Reserved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 171: ...CXP Subsystem Registers CON115 Version A 0 BitFlow Inc CYT 8 21 0_LINK_INT_ DEST R W CON115 1 0 Karbon CXP Cyton CXP TBD ...

Page 172: ...VF 8 0_CTL_REQ_FIFO_OVF 9 0_GPIO_NOMATCH 10 0_TRIG_NOMATCH 11 0_IOACK_UNKNOWN_TYPE 12 0_IOACK_NOMATCH 13 0_IOACK_UNEXPECTED_INT 14 0_IOACK_NOMATCH2 15 0_STRM_PKT_DROP 16 0_STRM_NOT_ENOUGH_DAT 17 0_STRM_TOO_MUCH_DAT 18 0_STRM_BAD_CRC 19 0_STRM_OVERFLOW 20 0_STRM_CORNER 21 0_SERDES_LOST_ALIGN 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved ...

Page 173: ...vice interrupt 0_CTL_ACK_ RCVD R W CON116 4 Karbon CXP Cyton CXP Control packet acknowledgement received from device interrupt 0_GPIO_RCVD R W CON116 5 Karbon CXP Cyton CXP GPIO received from device interrupt 0_TRIG_RCVD R W CON116 6 Karbon CXP Cyton CXP Trigger received from device interrupt 0_CTL_RSP_ FIFO_OVF R W CON116 7 Karbon CXP Cyton CXP Overflow detected in the control response fifo Devic...

Page 174: ...an IO acknowledgement from device interrupt 0_IOACK_ NOMATCH2 R W CON116 14 Karbon CXP Cyton CXP Problem decoding an IO acknowledgement from device interrupt 0_STRM_PKT_ DROP R W CON116 15 Karbon CXP Cyton CXP Problem decoding a stream packet header remainder of packet is dropped interrupt 0_STRM_NOT_ ENOUGH_DAT R W CON116 16 Karbon CXP Cyton CXP Not implemented reserved interrupt 0_STRM_TOO_ MUCH...

Page 175: ...isters CON116 Version A 0 BitFlow Inc CYT 8 25 0_STRM_ CORNER R W CON116 19 Karbon CXP Cyton CXP Not implemented reserved interrupt 0_SERDES_ LOST_ALIGN R W CON116 21 Karbon CXP Cyton CXP Serdes lost alignment interrupt ...

Page 176: ..._CTL_REQ_FIFO_OVF_M 9 0_GPIO_NOMATCH_M 10 0_TRIG_NOMATCH_M 11 0_IOACK_UNKNOWN_TYPE_M 12 0_IOACK_NOMATCH_M 13 0_IOACK_UNEXPECTED_INT_M 14 0_IOACK_NOMATCH2_M 15 0_STRM_PKT_DROP_M 16 0_STRM_NOT_ENOUGH_DAT_M 17 0_STRM_TOO_MUCH_DAT_M 18 0_STRM_BAD_CRC_M 19 0_STRM_OVERFLOW_M 20 0_STRM_CORNER_M 21 0_SERDES_LOST_ALIGN_M 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29...

Page 177: ... Mask for the 0_GPIO_ACK_RCVD_M interrupt 0_CTL_ACK_ RCVD_M R W CON117 4 Karbon CXP Cyton CXP Mask for the 0_CTL_ACK_RCVD_M interrupt 0_GPIO_RCVD_ M R W CON117 5 Karbon CXP Cyton CXP Mask for the 0_GPIO_RCVD_M interrupt 0_TRIG_RCVD_ M R W CON117 6 Karbon CXP Cyton CXP Mask for the 0_TRIG_RCVD_M interrupt 0_CTL_RSP_ FIFO_OVF_M R W CON117 7 Karbon CXP Cyton CXP Mask for the 0_CTL_RSP_FIFO_OVF_M inte...

Page 178: ...the 0_IOACK_UNEXPECTED_INT_M interrupt 0_IOACK_ NOMATCH2_M R W CON117 14 Karbon CXP Cyton CXP Mask for the 0_IOACK_NOMATCH2_M interrupt 0_STRM_PKT_ DROP_M R W CON117 15 Karbon CXP Cyton CXP Mask for the 0_STRM_PKT_DROP_M interrupt 0_STRM_NOT_ ENOUGH_DAT_ M R W CON117 16 Karbon CXP Cyton CXP Mask for the 0_STRM_NOT_ENOUGH_DAT_M interrupt 0_STRM_TOO_ MUCH_DAT_M R W CON117 17 Karbon CXP Cyton CXP Mas...

Page 179: ...0_CTL_REQ_FIFO_OVF_WP 9 0_GPIO_NOMATCH_WP 10 0_TRIG_NOMATCH_WP 11 0_IOACK_UNKNOWN_TYPE_WP 12 0_IOACK_NOMATCH_WP 13 0_IOACK_UNEXPECTED_INT_WP 14 0_IOACK_NOMATCH2_WP 15 0_STRM_PKT_DROP_WP 16 0_STRM_NOT_ENOUGH_DAT_WP 17 0_STRM_TOO_WPUCH_DAT_WP 18 0_STRM_BAD_CRC_WP 19 0_STRM_OVERFLOW_WP 20 0_STRM_CORNER_WP 21 0_SERDES_LOST_ALIGN_WP 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserve...

Page 180: ...0_GPIO_ACK_RCVD_WP interrupt 0_CTL_ACK_ RCVD_WP R W CON118 4 Karbon CXP Cyton CXP Write mask for the 0_CTL_ACK_RCVD_WP interrupt 0_GPIO_RCVD_ WP R W CON118 5 Karbon CXP Cyton CXP Write mask for the 0_GPIO_RCVD_WP interrupt 0_TRIG_RCVD_ WP R W CON118 6 Karbon CXP Cyton CXP Write mask for the 0_TRIG_RCVD_WP interrupt 0_CTL_RSP_ FIFO_OVF_WP R W CON118 7 Karbon CXP Cyton CXP Write mask for the 0_CTL_R...

Page 181: ...K_UNEXPECTED_INT_WP interrupt 0_IOACK_ NOMATCH2_WP R W CON118 14 Karbon CXP Cyton CXP Write mask for the 0_IOACK_NOMATCH2_WP interrupt 0_STRM_PKT_ DROP_WP R W CON118 15 Karbon CXP Cyton CXP Write mask for the 0_STRM_PKT_DROP_WP interrupt 0_STRM_NOT_ ENOUGH_DAT_ WP R W CON118 16 Karbon CXP Cyton CXP Write mask for the 0_STRM_NOT_ENOUGH_DAT_WP interrupt 0_STRM_TOO_ WPUCH_DAT_ WP R W CON118 17 Karbon...

Page 182: ...8 0_PKT_RCVD_CNT 9 0_PKT_RCVD_CNT 10 0_PKT_RCVD_CNT 11 0_PKT_RCVD_CNT 12 0_PKT_RCVD_CNT 13 0_PKT_RCVD_CNT 14 0_PKT_RCVD_CNT 15 0_PKT_RCVD_CNT 16 0_PKT_GNT_CNT 17 0_PKT_GNT_CNT 18 0_PKT_GNT_CNT 19 0_PKT_GNT_CNT 20 0_PKT_GNT_CNT 21 0_PKT_GNT_CNT 22 0_PKT_GNT_CNT 23 0_PKT_GNT_CNT 24 0_PKT_GNT_CNT 25 0_PKT_GNT_CNT 26 0_PKT_GNT_CNT 27 0_PKT_GNT_CNT 28 0_PKT_GNT_CNT 29 0_PKT_GNT_CNT 30 0_PKT_GNT_CNT 31 ...

Page 183: ...on CXP Number of CXP packets received on this link The entire register 31 0 is cleared on a write access of any value 0_PKT_GNT_ CNT RO CON120 31 16 Karbon CXP Cyton CXP Number of packets forwarded from this link to the Stream Assembler engine The entire register 31 0 is cleared on a write access of any value ...

Page 184: ...8 0_PKT_DROP_CNT 9 0_PKT_DROP_CNT 10 0_PKT_DROP_CNT 11 0_PKT_DROP_CNT 12 0_PKT_DROP_CNT 13 0_PKT_DROP_CNT 14 0_PKT_DROP_CNT 15 0_PKT_DROP_CNT 16 0_CRC_ERR_CNT 17 0_CRC_ERR_CNT 18 0_CRC_ERR_CNT 19 0_CRC_ERR_CNT 20 0_CRC_ERR_CNT 21 0_CRC_ERR_CNT 22 0_CRC_ERR_CNT 23 0_CRC_ERR_CNT 24 0_CRC_ERR_CNT 25 0_CRC_ERR_CNT 26 0_CRC_ERR_CNT 27 0_CRC_ERR_CNT 28 0_CRC_ERR_CNT 29 0_CRC_ERR_CNT 30 0_CRC_ERR_CNT 31 ...

Page 185: ...eader errors The entire register 31 0 is cleared on a write access of any value 0_CRC_ERR_ CNT RO CON121 31 16 Karbon CXP Cyton CXP Number of packets with crc errors These packets are not dropped because they most likely have a small data error and the majority of the frame can be recovered The entire register 31 0 is cleared on a write access of any value ...

Page 186: ...ved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 0_CXP_TRIG_ACK_CNT 25 0_CXP_TRIG_ACK_CNT 26 0_CXP_TRIG_ACK_CNT 27 0_CXP_TRIG_ACK_CNT 28 0_CXP_TRIG_ACK_CNT 29 0_CXP_TRIG_ACK_CNT 30 0_CXP_TRIG_ACK_CNT 31 0_CXP_TRIG_ACK_CNT ...

Page 187: ...ersion A 0 BitFlow Inc CYT 8 37 0_CXP_TRIG_ STATE RO CON122 0 Karbon CXP Cyton CXP Current state of the uplink CXP trigger signal 0_CXP_TRIG_ ACK_CNT RO CON122 31 24 Karbon CXP Cyton CXP Number of CXP trigger acknowledgements received ...

Page 188: ...ved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 0_CXP_GPIO_ACK_CNT 25 0_CXP_GPIO_ACK_CNT 26 0_CXP_GPIO_ACK_CNT 27 0_CXP_GPIO_ACK_CNT 28 0_CXP_GPIO_ACK_CNT 29 0_CXP_GPIO_ACK_CNT 30 0_CXP_GPIO_ACK_CNT 31 0_CXP_GPIO_ACK_CNT ...

Page 189: ...123 Version A 0 BitFlow Inc CYT 8 39 0_CXP_GPIO_ STATE RO CON123 0 Karbon CXP Cyton CXP Current state up of the uplink CXP GPIO bus 0_CXP_GPIO_ ACK_CNT RO CON123 31 24 Karbon CXP Cyton CXP Number of GPIO acknowledgements received ...

Page 190: ...LINK_SPEED 5 0_LINK_SPEED 6 0_LINK_SPEED 7 0_LINK_SPEED 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 191: ...CXP Subsystem Registers CON126 Version A 0 BitFlow Inc CYT 8 41 0_LINK_SPEED RO CON126 7 0 Karbon CXP Cyton CXP Describe 0_LINK_SPEED ...

Page 192: ...TATE 5 0_SERDES_STATE 6 0_SERDES_STATE 7 Reserved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 0_SERDES_ALIGNED 31 0_SERDERS_SIGNALDETECT ...

Page 193: ...nc CYT 8 43 0_SERDES_ STATE RO CON127 6 0 Karbon CXP Cyton CXP Describe 0_SERDES_STATE 0_SERDES_ ALIGNED RO CON127 30 Karbon CXP Cyton CXP Describe 0_SERDES_ALIGNED 0_SERDERS_ SIGNALDETECT RO CON127 31 Karbon CXP Cyton CXP Describe 0_SERDERS_SIGNALDETECT ...

Page 194: ...d 4 Reserved 5 Reserved 6 Reserved 7 Reserved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 195: ... Inc CYT 8 45 0_RAW_DATA_ MODE R W CON128 0 Karbon CXP Cyton CXP Enable raw capture mode This mode captures raw data from the CXP link without any processing 0_REMOVE_ IDLES R W CON128 1 Karbon CXP Cyton CXP Remove CXP idle packets from the raw capture ...

Page 196: ... 10 0_SERDES_ERROR_CODE 11 0_SERDES_ERROR_CODE 12 0_SERDES_ERROR_CODE 13 0_SERDES_ERROR_CODE 14 0_SERDES_ERROR_CODE 15 0_SERDES_ERROR_CODE 16 0_SERDES_ERROR_CODE 17 0_SERDES_ERROR_CODE 18 0_SERDES_ERROR_CODE 19 0_SERDES_ERROR_CODE 20 0_SERDES_ERROR_CODE 21 0_SERDES_ERROR_CODE 22 0_SERDES_ERROR_CODE 23 0_SERDES_ERROR_CODE 24 0_SERDES_ERROR_CODE 25 0_SERDES_ERROR_CODE 26 0_SERDES_ERROR_CODE 27 0_SER...

Page 197: ...CXP Subsystem Registers CON131 Version A 0 BitFlow Inc CYT 8 47 0_SERDES_ ERROR_CODE RO CON131 30 0 Karbon CXP Cyton CXP Describe 0_SERDES_ERROR_CODE ...

Page 198: ...P_UNDER_LATCH 10 1_POCXP_24V_OK 11 Reserved 12 1_POCXP_STATE 13 1_POCXP_OVR_AUTO_RESTART 14 1_POCXP_SENSE_BYPASS 15 1_ENABLE_POCXP_SYSTEM 16 1_POCXP_CURRENT_LATCH 17 1_POCXP_CURRENT_LATCH 18 1_POCXP_CURRENT_LATCH 19 1_POCXP_CURRENT_LATCH 20 1_POCXP_CURRENT_LATCH 21 1_POCXP_CURRENT_LATCH 22 1_POCXP_CURRENT_LATCH 23 1_POCXP_CURRENT_LATCH 24 1_POCXP_CURRENT 25 1_POCXP_CURRENT 26 1_POCXP_CURRENT 27 1_...

Page 199: ...on of 0_POCXP_CAM_IS_POCXP 1_POCXP_ SHORT_ DETECTED RO CON136 4 Karbon CXP Cyton CXP See description of 0_POCXP_SHORT_DETECTED 1_POCXP_ OPEN_ DETECTED RO CON136 5 Karbon CXP Cyton CXP See description of 0_POCXP_OPEN_DETECTED 1_POCXP_ OVER_ DETECTED RO CON136 6 Karbon CXP Cyton CXP See description of 0_POCXP_OVER_DETECTED 1_POCXP_ OVER_LATCH RO CON136 7 Karbon CXP Cyton CXP See description of 0_POC...

Page 200: ...36 13 Karbon CXP Cyton CXP See description of 0_POCXP_OVR_AUTO_RESTART 1_POCXP_ SENSE_BYPASS RW CON136 14 Karbon CXP Cyton CXP See description of 0_POCXP_SENSE_BYPASS 1_ENABLE_ POCXP_SYSTEM RW CON136 15 Karbon CXP Cyton CXP See description of 0_ENABLE_POCXP_SYSTEM 1_POCXP_ CURRENT_ LATCH RO CON136 23 16 Karbon CXP Cyton CXP See description of 0_POCXP_CURRENT_LATCH 1_POCXP_ CURRENT RO CON136 31 24 ...

Page 201: ..._TIMER 10 1_POCXP_OVER_TIMER 11 1_POCXP_OVER_TIMER 12 1_POCXP_OVER_TIMER 13 1_POCXP_OVER_TIMER 14 1_POCXP_OVER_TIMER 15 1_POCXP_OVER_TIMER 16 1_POCXP_OVER_TIMER 17 1_POCXP_OVER_TIMER 18 1_POCXP_OVER_TIMER 19 1_POCXP_OVER_TIMER 20 1_POCXP_OVER_TIMER 21 1_POCXP_OVER_TIMER 22 1_POCXP_OVER_TIMER 23 1_POCXP_OVER_TIMER 24 1_POCXP_OVER_TIMER 25 1_POCXP_OVER_TIMER 26 1_POCXP_OVER_TIMER 27 1_POCXP_OVER_TIM...

Page 202: ...CON137 The Cyton CXP CYT 8 52 BitFlow Inc Version A 0 1_POCXP_ OVER_TIMER R W CON137 31 0 Karbon CXP Cyton CXP See description of 0_POCXP_OVER_TIMER ...

Page 203: ... 10 1_POCXP_UNDER_TIMER 11 1_POCXP_UNDER_TIMER 12 1_POCXP_UNDER_TIMER 13 1_POCXP_UNDER_TIMER 14 1_POCXP_UNDER_TIMER 15 1_POCXP_UNDER_TIMER 16 1_POCXP_UNDER_TIMER 17 1_POCXP_UNDER_TIMER 18 1_POCXP_UNDER_TIMER 19 1_POCXP_UNDER_TIMER 20 1_POCXP_UNDER_TIMER 21 1_POCXP_UNDER_TIMER 22 1_POCXP_UNDER_TIMER 23 1_POCXP_UNDER_TIMER 24 1_POCXP_UNDER_TIMER 25 1_POCXP_UNDER_TIMER 26 1_POCXP_UNDER_TIMER 27 1_POC...

Page 204: ...CON138 The Cyton CXP CYT 8 54 BitFlow Inc Version A 0 1_POCXP_ UNDER_TIMER R W CON138 31 0 Karbon CXP Cyton CXP See description of 0_POCXP_UNDER_TIMER ...

Page 205: ...M_RCV_FIFO_SIZE 11 1_COM_RCV_FIFO_SIZE 12 1_COM_RCV_FIFO_SIZE 13 1_COM_RCV_FIFO_SIZE 14 1_COM_RCV_FIFO_SIZE 15 1_COM_RCV_FIFO_SIZE 16 1_COM_SEND_FIFO_SIZE 17 1_COM_SEND_FIFO_SIZE 18 1_COM_SEND_FIFO_SIZE 19 1_COM_SEND_FIFO_SIZE 20 1_COM_SEND_FIFO_SIZE 21 1_COM_SEND_FIFO_SIZE 22 1_COM_SEND_FIFO_SIZE 23 1_COM_SEND_FIFO_SIZE 24 1_COM_SEND_FIFO_SIZE 25 1_COM_SEND_FIFO_SIZE 26 1_COM_SEND_FIFO_SIZE 27 1_...

Page 206: ...T 8 56 BitFlow Inc Version A 0 1_COM_RCV_ FIFO_SIZE RO CON139 15 0 Karbon CXP Cyton CXP See description of 0_COM_RCV_FIFO_SIZE 1_COM_SEND_ FIFO_SIZE RO CON139 31 16 Karbon CXP Cyton CXP See description of 0_COM_SEND_FIFO_SIZE ...

Page 207: ...1 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 1_COM_SEND_FIFO_CNT 17 1_COM_SEND_FIFO_CNT 18 1_COM_SEND_FIFO_CNT 19 1_COM_SEND_FIFO_CNT 20 1_COM_SEND_FIFO_CNT 21 1_COM_SEND_FIFO_CNT 22 1_COM_SEND_FIFO_CNT 23 1_COM_SEND_FIFO_CNT 24 1_COM_SEND_FIFO_CNT 25 1_COM_SEND_FIFO_CNT 26 1_COM_SEND_FIFO_CNT 27 1_COM_SEND_FIFO_CNT 28 1_COM_SEND_FIFO_CNT 29 1_COM_SEND_FIFO_CNT 30 1_COM_SEND_FIFO_...

Page 208: ...END_ FIFO_CLR WO CON140 0 Karbon CXP Cyton CXP See description of 0_COM_SEND_FIFO_CLR 1_COM_SEND_ GO WO CON140 1 Karbon CXP Cyton CXP See description of 0_COM_SEND_GO 1_COM_SEND_ FIFO_CNT RO CON140 31 16 Karbon CXP Cyton CXP See description of 0_COM_SEND_FIFO_CNT ...

Page 209: ...D_DATA 9 1_COM_SEND_DATA 10 1_COM_SEND_DATA 11 1_COM_SEND_DATA 12 1_COM_SEND_DATA 13 1_COM_SEND_DATA 14 1_COM_SEND_DATA 15 1_COM_SEND_DATA 16 1_COM_SEND_DATA 17 1_COM_SEND_DATA 18 1_COM_SEND_DATA 19 1_COM_SEND_DATA 20 1_COM_SEND_DATA 21 1_COM_SEND_DATA 22 1_COM_SEND_DATA 23 1_COM_SEND_DATA 24 1_COM_SEND_DATA 25 1_COM_SEND_DATA 26 1_COM_SEND_DATA 27 1_COM_SEND_DATA 28 1_COM_SEND_DATA 29 1_COM_SEND_...

Page 210: ...CON141 The Cyton CXP CYT 8 60 BitFlow Inc Version A 0 1_COM_SEND_ DATA R W CON141 31 0 Karbon CXP Cyton CXP See description of 0_COM_SEND_DATA ...

Page 211: ...ved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 1_COM_RCV_FIFO_CNT 17 1_COM_RCV_FIFO_CNT 18 1_COM_RCV_FIFO_CNT 19 1_COM_RCV_FIFO_CNT 20 1_COM_RCV_FIFO_CNT 21 1_COM_RCV_FIFO_CNT 22 1_COM_RCV_FIFO_CNT 23 1_COM_RCV_FIFO_CNT 24 1_COM_RCV_FIFO_CNT 25 1_COM_RCV_FIFO_CNT 26 1_COM_RCV_FIFO_CNT 27 1_COM_RCV_FIFO_CNT 28 1_COM_RCV_FIFO_CNT 29 1_COM_RCV_FIFO_CNT 30 1_COM_RCV_FIFO_CNT 31 1_C...

Page 212: ...P CYT 8 62 BitFlow Inc Version A 0 1_COM_RCV_ FIFO_CLR WO CON142 0 Karbon CXP Cyton CXP See description of 0_COM_RCV_FIFO_CLR 1_COM_RCV_ FIFO_CNT RO CON142 31 16 Karbon CXP Cyton CXP See description of 0_COM_RCV_FIFO_CNT ...

Page 213: ..._COM_RCV_DATA 9 1_COM_RCV_DATA 10 1_COM_RCV_DATA 11 1_COM_RCV_DATA 12 1_COM_RCV_DATA 13 1_COM_RCV_DATA 14 1_COM_RCV_DATA 15 1_COM_RCV_DATA 16 1_COM_RCV_DATA 17 1_COM_RCV_DATA 18 1_COM_RCV_DATA 19 1_COM_RCV_DATA 20 1_COM_RCV_DATA 21 1_COM_RCV_DATA 22 1_COM_RCV_DATA 23 1_COM_RCV_DATA 24 1_COM_RCV_DATA 25 1_COM_RCV_DATA 26 1_COM_RCV_DATA 27 1_COM_RCV_DATA 28 1_COM_RCV_DATA 29 1_COM_RCV_DATA 30 1_COM_...

Page 214: ...CON143 The Cyton CXP CYT 8 64 BitFlow Inc Version A 0 1_COM_RCV_ DATA RO CON143 31 0 Karbon CXP Cyton CXP See description of 0_COM_RCV_DATA ...

Page 215: ...eserved 4 Reserved 5 Reserved 6 Reserved 7 Reserved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 216: ...CON147 The Cyton CXP CYT 8 66 BitFlow Inc Version A 0 1_LINK_INT_ DEST R W CON147 1 0 Karbon CXP Cyton CXP See description of 0_LINK_INT_DEST ...

Page 217: ...IFO_OVF 8 1_CTL_REQ_FIFO_OVF 9 1_GPIO_NOMATCH 10 1_TRIG_NOMATCH 11 1_IOACK_UNKNOWN_TYPE 12 1_IOACK_NOMATCH 13 1_IOACK_UNEXPECTED_INT 14 1_IOACK_NOMATCH2 15 1_STRM_PKT_DROP 16 1_STRM_NOT_ENOUGH_DAT 17 1_STRM_TOO_MUCH_DAT 18 1_STRM_BAD_CRC 19 1_STRM_OVERFLOW 20 1_STRM_CORNER 21 1_SERDES_LOST_ALIGN 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Rese...

Page 218: ... Cyton CXP See description of 0_GPIO_ACK_RCVD 1_CTL_ACK_ RCVD R W CON148 4 Karbon CXP Cyton CXP See description of 0_CTL_ACK_RCVD 1_GPIO_RCVD R W CON148 5 Karbon CXP Cyton CXP See description of 0_GPIO_RCVD 1_TRIG_RCVD R W CON148 6 Karbon CXP Cyton CXP See description of 0_TRIG_RCVD 1_CTL_RSP_ FIFO_OVF R W CON148 7 Karbon CXP Cyton CXP See description of 0_CTL_RSP_FIFO_OVF 1_CTL_REQ_ FIFO_OVF R W ...

Page 219: ...n CXP See description of 0_IOACK_UNEXPECTED_INT 1_IOACK_ NOMATCH2 R W CON148 14 Karbon CXP Cyton CXP See description of 0_IOACK_NOMATCH2 1_STRM_PKT_ DROP R W CON148 15 Karbon CXP Cyton CXP See description of 0_STRM_PKT_DROP 1_STRM_NOT_ ENOUGH_DAT R W CON148 16 Karbon CXP Cyton CXP See description of 0_STRM_NOT_ENOUGH_DAT 1_STRM_TOO_ MUCH_DAT R W CON148 17 Karbon CXP Cyton CXP See description of 0_...

Page 220: ..._CTL_REQ_FIFO_OVF_M 9 1_GPIO_NOMATCH_M 10 1_TRIG_NOMATCH_M 11 1_IOACK_UNKNOWN_TYPE_M 12 1_IOACK_NOMATCH_M 13 1_IOACK_UNEXPECTED_INT_M 14 1_IOACK_NOMATCH2_M 15 1_STRM_PKT_DROP_M 16 1_STRM_NOT_ENOUGH_DAT_M 17 1_STRM_TOO_MUCH_DAT_M 18 1_STRM_BAD_CRC_M 19 1_STRM_OVERFLOW_M 20 1_STRM_CORNER_M 21 1_SERDES_LOST_ALIGN_M 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29...

Page 221: ...yton CXP See description of 0_GPIO_ACK_RCVD_M 1_CTL_ACK_ RCVD_M R W CON149 4 Karbon CXP Cyton CXP See description of 0_CTL_ACK_RCVD_M 1_GPIO_RCVD_ M R W CON149 5 Karbon CXP Cyton CXP See description of 0_GPIO_RCVD_M 1_TRIG_RCVD_ M R W CON149 6 Karbon CXP Cyton CXP See description of 0_TRIG_RCVD_M 1_CTL_RSP_ FIFO_OVF_M R W CON149 7 Karbon CXP Cyton CXP See description of 0_CTL_RSP_FIFO_OVF_M 1_CTL_...

Page 222: ...escription of 0_IOACK_UNEXPECTED_INT_M 1_IOACK_ NOMATCH2_M R W CON149 14 Karbon CXP Cyton CXP See description of 0_IOACK_NOMATCH2_M 1_STRM_PKT_ DROP_M R W CON149 15 Karbon CXP Cyton CXP See description of 0_STRM_PKT_DROP_M 1_STRM_NOT_ ENOUGH_DAT_ M R W CON149 16 Karbon CXP Cyton CXP See description of 0_STRM_NOT_ENOUGH_DAT_M 1_STRM_TOO_ MUCH_DAT_M R W CON149 17 Karbon CXP Cyton CXP See description...

Page 223: ...1_CTL_REQ_FIFO_OVF_WP 9 1_GPIO_NOMATCH_WP 10 1_TRIG_NOMATCH_WP 11 1_IOACK_UNKNOWN_TYPE_WP 12 1_IOACK_NOMATCH_WP 13 1_IOACK_UNEXPECTED_INT_WP 14 1_IOACK_NOMATCH2_WP 15 1_STRM_PKT_DROP_WP 16 1_STRM_NOT_ENOUGH_DAT_WP 17 1_STRM_TOO_WPUCH_DAT_WP 18 1_STRM_BAD_CRC_WP 19 1_STRM_OVERFLOW_WP 20 1_STRM_CORNER_WP 21 1_SERDES_LOST_ALIGN_WP 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserve...

Page 224: ... See description of 0_GPIO_ACK_RCVD_WP 1_CTL_ACK_ RCVD_WP R W CON150 4 Karbon CXP Cyton CXP See description of 0_CTL_ACK_RCVD_WP 1_GPIO_RCVD_ WP R W CON150 5 Karbon CXP Cyton CXP See description of 0_GPIO_RCVD_WP 1_TRIG_RCVD_ WP R W CON150 6 Karbon CXP Cyton CXP See description of 0_TRIG_RCVD_WP 1_CTL_RSP_ FIFO_OVF_WP R W CON150 7 Karbon CXP Cyton CXP See description of 0_CTL_RSP_FIFO_OVF_WP 1_CTL...

Page 225: ...escription of 0_IOACK_UNEXPECTED_INT_WP 1_IOACK_ NOMATCH2_WP R W CON150 14 Karbon CXP Cyton CXP See description of 0_IOACK_NOMATCH2_WP 1_STRM_PKT_ DROP_WP R W CON150 15 Karbon CXP Cyton CXP See description of 0_STRM_PKT_DROP_WP 1_STRM_NOT_ ENOUGH_DAT_ WP R W CON150 16 Karbon CXP Cyton CXP See description of 0_STRM_NOT_ENOUGH_DAT_WP 1_STRM_TOO_ WPUCH_DAT_ WP R W CON150 17 Karbon CXP Cyton CXP See d...

Page 226: ...8 1_PKT_RCVD_CNT 9 1_PKT_RCVD_CNT 10 1_PKT_RCVD_CNT 11 1_PKT_RCVD_CNT 12 1_PKT_RCVD_CNT 13 1_PKT_RCVD_CNT 14 1_PKT_RCVD_CNT 15 1_PKT_RCVD_CNT 16 1_PKT_GNT_CNT 17 1_PKT_GNT_CNT 18 1_PKT_GNT_CNT 19 1_PKT_GNT_CNT 20 1_PKT_GNT_CNT 21 1_PKT_GNT_CNT 22 1_PKT_GNT_CNT 23 1_PKT_GNT_CNT 24 1_PKT_GNT_CNT 25 1_PKT_GNT_CNT 26 1_PKT_GNT_CNT 27 1_PKT_GNT_CNT 28 1_PKT_GNT_CNT 29 1_PKT_GNT_CNT 30 1_PKT_GNT_CNT 31 ...

Page 227: ...gisters CON152 Version A 0 BitFlow Inc CYT 8 77 1_PKT_RCVD_ CNT RO CON152 15 0 Karbon CXP Cyton CXP See description of 0_PKT_RCVD_CNT 1_PKT_GNT_ CNT RO CON152 31 16 Karbon CXP Cyton CXP See description of 0_PKT_GNT_CNT ...

Page 228: ...8 1_PKT_DROP_CNT 9 1_PKT_DROP_CNT 10 1_PKT_DROP_CNT 11 1_PKT_DROP_CNT 12 1_PKT_DROP_CNT 13 1_PKT_DROP_CNT 14 1_PKT_DROP_CNT 15 1_PKT_DROP_CNT 16 1_CRC_ERR_CNT 17 1_CRC_ERR_CNT 18 1_CRC_ERR_CNT 19 1_CRC_ERR_CNT 20 1_CRC_ERR_CNT 21 1_CRC_ERR_CNT 22 1_CRC_ERR_CNT 23 1_CRC_ERR_CNT 24 1_CRC_ERR_CNT 25 1_CRC_ERR_CNT 26 1_CRC_ERR_CNT 27 1_CRC_ERR_CNT 28 1_CRC_ERR_CNT 29 1_CRC_ERR_CNT 30 1_CRC_ERR_CNT 31 ...

Page 229: ...gisters CON153 Version A 0 BitFlow Inc CYT 8 79 1_PKT_DROP_ CNT RO CON153 15 0 Karbon CXP Cyton CXP See description of 0_PKT_DROP_CNT 1_CRC_ERR_ CNT RO CON153 31 16 Karbon CXP Cyton CXP See description of 0_CRC_ERR_CNT ...

Page 230: ...ved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 1_CXP_TRIG_ACK_CNT 25 1_CXP_TRIG_ACK_CNT 26 1_CXP_TRIG_ACK_CNT 27 1_CXP_TRIG_ACK_CNT 28 1_CXP_TRIG_ACK_CNT 29 1_CXP_TRIG_ACK_CNT 30 1_CXP_TRIG_ACK_CNT 31 1_CXP_TRIG_ACK_CNT ...

Page 231: ...s CON154 Version A 0 BitFlow Inc CYT 8 81 1_CXP_TRIG_ STATE RO CON154 0 Karbon CXP Cyton CXP See description of 0_CXP_TRIG_STATE 1_CXP_TRIG_ ACK_CNT RO CON154 31 24 Karbon CXP Cyton CXP See description of 0_CXP_TRIG_ACK_CNT ...

Page 232: ...ved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 1_CXP_GPIO_ACK_CNT 25 1_CXP_GPIO_ACK_CNT 26 1_CXP_GPIO_ACK_CNT 27 1_CXP_GPIO_ACK_CNT 28 1_CXP_GPIO_ACK_CNT 29 1_CXP_GPIO_ACK_CNT 30 1_CXP_GPIO_ACK_CNT 31 1_CXP_GPIO_ACK_CNT ...

Page 233: ...s CON155 Version A 0 BitFlow Inc CYT 8 83 1_CXP_GPIO_ STATE RO CON155 0 Karbon CXP Cyton CXP See description of 0_CXP_GPIO_STATE 1_CXP_GPIO_ ACK_CNT RO CON155 31 24 Karbon CXP Cyton CXP See description of 0_CXP_GPIO_ACK_CNT ...

Page 234: ...LINK_SPEED 5 1_LINK_SPEED 6 1_LINK_SPEED 7 1_LINK_SPEED 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 235: ...CXP Subsystem Registers CON158 Version A 0 BitFlow Inc CYT 8 85 1_LINK_SPEED RO CON158 7 0 Karbon CXP Cyton CXP See description of 0_LINK_SPEED ...

Page 236: ...TATE 5 1_SERDES_STATE 6 1_SERDES_STATE 7 Reserved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 1_SERDES_ALIGNED 31 1_SERDERS_SIGNALDETECT ...

Page 237: ...ERDES_ STATE RO CON159 6 0 Karbon CXP Cyton CXP See description of 0_SERDES_STATE 1_SERDES_ ALIGNED RO CON159 30 Karbon CXP Cyton CXP See description of 0_SERDES_ALIGNED 1_SERDERS_ SIGNALDETECT RO CON159 31 Karbon CXP Cyton CXP See description of 0_SERDERS_SIGNALDETECT ...

Page 238: ...d 4 Reserved 5 Reserved 6 Reserved 7 Reserved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 239: ...gisters CON160 Version A 0 BitFlow Inc CYT 8 89 1_RAW_DATA_ MODE R W CON160 0 Karbon CXP Cyton CXP See description of 0_RAW_DATA_MODE 1_REMOVE_ IDLES R W CON160 1 Karbon CXP Cyton CXP See description of 0_REMOVE_IDLES ...

Page 240: ... 10 1_SERDES_ERROR_CODE 11 1_SERDES_ERROR_CODE 12 1_SERDES_ERROR_CODE 13 1_SERDES_ERROR_CODE 14 1_SERDES_ERROR_CODE 15 1_SERDES_ERROR_CODE 16 1_SERDES_ERROR_CODE 17 1_SERDES_ERROR_CODE 18 1_SERDES_ERROR_CODE 19 1_SERDES_ERROR_CODE 20 1_SERDES_ERROR_CODE 21 1_SERDES_ERROR_CODE 22 1_SERDES_ERROR_CODE 23 1_SERDES_ERROR_CODE 24 1_SERDES_ERROR_CODE 25 1_SERDES_ERROR_CODE 26 1_SERDES_ERROR_CODE 27 1_SER...

Page 241: ...CXP Subsystem Registers CON163 Version A 0 BitFlow Inc CYT 8 91 1_SERDES_ ERROR_CODE RO CON163 30 0 Karbon CXP Cyton CXP See description of 0_SERDES_ERROR_CODE ...

Page 242: ...P_UNDER_LATCH 10 2_POCXP_24V_OK 11 Reserved 12 2_POCXP_STATE 13 2_POCXP_OVR_AUTO_RESTART 14 2_POCXP_SENSE_BYPASS 15 2_ENABLE_POCXP_SYSTEM 16 2_POCXP_CURRENT_LATCH 17 2_POCXP_CURRENT_LATCH 18 2_POCXP_CURRENT_LATCH 19 2_POCXP_CURRENT_LATCH 20 2_POCXP_CURRENT_LATCH 21 2_POCXP_CURRENT_LATCH 22 2_POCXP_CURRENT_LATCH 23 2_POCXP_CURRENT_LATCH 24 2_POCXP_CURRENT 25 2_POCXP_CURRENT 26 2_POCXP_CURRENT 27 2_...

Page 243: ...ion of 0_POCXP_CAM_IS_POCXP 2_POCXP_ SHORT_ DETECTED RO CON168 4 Karbon CXP Cyton CXP See description of 0_POCXP_SHORT_DETECTED 2_POCXP_ OPEN_ DETECTED RO CON168 5 Karbon CXP Cyton CXP See description of 0_POCXP_OPEN_DETECTED 2_POCXP_ OVER_ DETECTED RO CON168 6 Karbon CXP Cyton CXP See description of 0_POCXP_OVER_DETECTED 2_POCXP_ OVER_LATCH RO CON168 7 Karbon CXP Cyton CXP See description of 0_PO...

Page 244: ...68 13 Karbon CXP Cyton CXP See description of 0_POCXP_OVR_AUTO_RESTART 2_POCXP_ SENSE_BYPASS RW CON168 14 Karbon CXP Cyton CXP See description of 0_POCXP_SENSE_BYPASS 2_ENABLE_ POCXP_SYSTEM RW CON168 15 Karbon CXP Cyton CXP See description of 0_ENABLE_POCXP_SYSTEM 2_POCXP_ CURRENT_ LATCH RO CON168 23 16 Karbon CXP Cyton CXP See description of 0_POCXP_CURRENT_LATCH 2_POCXP_ CURRENT RO CON168 31 24 ...

Page 245: ..._TIMER 10 2_POCXP_OVER_TIMER 11 2_POCXP_OVER_TIMER 12 2_POCXP_OVER_TIMER 13 2_POCXP_OVER_TIMER 14 2_POCXP_OVER_TIMER 15 2_POCXP_OVER_TIMER 16 2_POCXP_OVER_TIMER 17 2_POCXP_OVER_TIMER 18 2_POCXP_OVER_TIMER 19 2_POCXP_OVER_TIMER 20 2_POCXP_OVER_TIMER 21 2_POCXP_OVER_TIMER 22 2_POCXP_OVER_TIMER 23 2_POCXP_OVER_TIMER 24 2_POCXP_OVER_TIMER 25 2_POCXP_OVER_TIMER 26 2_POCXP_OVER_TIMER 27 2_POCXP_OVER_TIM...

Page 246: ...CON169 The Cyton CXP CYT 8 96 BitFlow Inc Version A 0 2_POCXP_ OVER_TIMER R W CON169 31 0 Karbon CXP Cyton CXP See description of 0_POCXP_OVER_TIMER ...

Page 247: ... 10 2_POCXP_UNDER_TIMER 11 2_POCXP_UNDER_TIMER 12 2_POCXP_UNDER_TIMER 13 2_POCXP_UNDER_TIMER 14 2_POCXP_UNDER_TIMER 15 2_POCXP_UNDER_TIMER 16 2_POCXP_UNDER_TIMER 17 2_POCXP_UNDER_TIMER 18 2_POCXP_UNDER_TIMER 19 2_POCXP_UNDER_TIMER 20 2_POCXP_UNDER_TIMER 21 2_POCXP_UNDER_TIMER 22 2_POCXP_UNDER_TIMER 23 2_POCXP_UNDER_TIMER 24 2_POCXP_UNDER_TIMER 25 2_POCXP_UNDER_TIMER 26 2_POCXP_UNDER_TIMER 27 2_POC...

Page 248: ...CON170 The Cyton CXP CYT 8 98 BitFlow Inc Version A 0 2_POCXP_ UNDER_TIMER R W CON170 31 0 Karbon CXP Cyton CXP See description of 0_POCXP_UNDER_TIMER ...

Page 249: ...M_RCV_FIFO_SIZE 11 2_COM_RCV_FIFO_SIZE 12 2_COM_RCV_FIFO_SIZE 13 2_COM_RCV_FIFO_SIZE 14 2_COM_RCV_FIFO_SIZE 15 2_COM_RCV_FIFO_SIZE 16 2_COM_SEND_FIFO_SIZE 17 2_COM_SEND_FIFO_SIZE 18 2_COM_SEND_FIFO_SIZE 19 2_COM_SEND_FIFO_SIZE 20 2_COM_SEND_FIFO_SIZE 21 2_COM_SEND_FIFO_SIZE 22 2_COM_SEND_FIFO_SIZE 23 2_COM_SEND_FIFO_SIZE 24 2_COM_SEND_FIFO_SIZE 25 2_COM_SEND_FIFO_SIZE 26 2_COM_SEND_FIFO_SIZE 27 2_...

Page 250: ... 8 100 BitFlow Inc Version A 0 2_COM_RCV_ FIFO_SIZE RO CON171 15 0 Karbon CXP Cyton CXP See description of 0_COM_RCV_FIFO_SIZE 2_COM_SEND_ FIFO_SIZE RO CON171 31 16 Karbon CXP Cyton CXP See description of 0_COM_SEND_FIFO_SIZE ...

Page 251: ...1 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 2_COM_SEND_FIFO_CNT 17 2_COM_SEND_FIFO_CNT 18 2_COM_SEND_FIFO_CNT 19 2_COM_SEND_FIFO_CNT 20 2_COM_SEND_FIFO_CNT 21 2_COM_SEND_FIFO_CNT 22 2_COM_SEND_FIFO_CNT 23 2_COM_SEND_FIFO_CNT 24 2_COM_SEND_FIFO_CNT 25 2_COM_SEND_FIFO_CNT 26 2_COM_SEND_FIFO_CNT 27 2_COM_SEND_FIFO_CNT 28 2_COM_SEND_FIFO_CNT 29 2_COM_SEND_FIFO_CNT 30 2_COM_SEND_FIFO_...

Page 252: ...END_ FIFO_CLR WO CON172 0 Karbon CXP Cyton CXP See description of 0_COM_SEND_FIFO_CLR 2_COM_SEND_ GO WO CON172 1 Karbon CXP Cyton CXP See description of 0_COM_SEND_GO 2_COM_SEND_ FIFO_CNT RO CON172 31 16 Karbon CXP Cyton CXP See description of 0_COM_SEND_FIFO_CNT ...

Page 253: ...D_DATA 9 2_COM_SEND_DATA 10 2_COM_SEND_DATA 11 2_COM_SEND_DATA 12 2_COM_SEND_DATA 13 2_COM_SEND_DATA 14 2_COM_SEND_DATA 15 2_COM_SEND_DATA 16 2_COM_SEND_DATA 17 2_COM_SEND_DATA 18 2_COM_SEND_DATA 19 2_COM_SEND_DATA 20 2_COM_SEND_DATA 21 2_COM_SEND_DATA 22 2_COM_SEND_DATA 23 2_COM_SEND_DATA 24 2_COM_SEND_DATA 25 2_COM_SEND_DATA 26 2_COM_SEND_DATA 27 2_COM_SEND_DATA 28 2_COM_SEND_DATA 29 2_COM_SEND_...

Page 254: ...CON173 The Cyton CXP CYT 8 104 BitFlow Inc Version A 0 2_COM_SEND_ DATA R W CON173 31 0 Karbon CXP Cyton CXP See description of 0_COM_SEND_DATA ...

Page 255: ...ved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 2_COM_RCV_FIFO_CNT 17 2_COM_RCV_FIFO_CNT 18 2_COM_RCV_FIFO_CNT 19 2_COM_RCV_FIFO_CNT 20 2_COM_RCV_FIFO_CNT 21 2_COM_RCV_FIFO_CNT 22 2_COM_RCV_FIFO_CNT 23 2_COM_RCV_FIFO_CNT 24 2_COM_RCV_FIFO_CNT 25 2_COM_RCV_FIFO_CNT 26 2_COM_RCV_FIFO_CNT 27 2_COM_RCV_FIFO_CNT 28 2_COM_RCV_FIFO_CNT 29 2_COM_RCV_FIFO_CNT 30 2_COM_RCV_FIFO_CNT 31 2_C...

Page 256: ...P CYT 8 106 BitFlow Inc Version A 0 2_COM_RCV_ FIFO_CLR WO CON174 0 Karbon CXP Cyton CXP See description of 0_COM_RCV_FIFO_CLR 2_COM_RCV_ FIFO_CNT RO CON174 31 16 Karbon CXP Cyton CXP See description of 0_COM_RCV_FIFO_CNT ...

Page 257: ..._COM_RCV_DATA 9 2_COM_RCV_DATA 10 2_COM_RCV_DATA 11 2_COM_RCV_DATA 12 2_COM_RCV_DATA 13 2_COM_RCV_DATA 14 2_COM_RCV_DATA 15 2_COM_RCV_DATA 16 2_COM_RCV_DATA 17 2_COM_RCV_DATA 18 2_COM_RCV_DATA 19 2_COM_RCV_DATA 20 2_COM_RCV_DATA 21 2_COM_RCV_DATA 22 2_COM_RCV_DATA 23 2_COM_RCV_DATA 24 2_COM_RCV_DATA 25 2_COM_RCV_DATA 26 2_COM_RCV_DATA 27 2_COM_RCV_DATA 28 2_COM_RCV_DATA 29 2_COM_RCV_DATA 30 2_COM_...

Page 258: ...CON175 The Cyton CXP CYT 8 108 BitFlow Inc Version A 0 2_COM_RCV_ DATA RO CON175 31 0 Karbon CXP Cyton CXP See description of 0_COM_RCV_DATA ...

Page 259: ...eserved 4 Reserved 5 Reserved 6 Reserved 7 Reserved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 260: ...CON179 The Cyton CXP CYT 8 110 BitFlow Inc Version A 0 2_LINK_INT_ DEST R W CON179 1 0 Karbon CXP Cyton CXP See description of 0_LINK_INT_DEST ...

Page 261: ...IFO_OVF 8 2_CTL_REQ_FIFO_OVF 9 2_GPIO_NOMATCH 10 2_TRIG_NOMATCH 11 2_IOACK_UNKNOWN_TYPE 12 2_IOACK_NOMATCH 13 2_IOACK_UNEXPECTED_INT 14 2_IOACK_NOMATCH2 15 2_STRM_PKT_DROP 16 2_STRM_NOT_ENOUGH_DAT 17 2_STRM_TOO_MUCH_DAT 18 2_STRM_BAD_CRC 19 2_STRM_OVERFLOW 20 2_STRM_CORNER 21 2_SERDES_LOST_ALIGN 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Rese...

Page 262: ...P Cyton CXP See description of 0_GPIO_ACK_RCVD 2_CTL_ACK_ RCVD R W CON180 4 Karbon CXP Cyton CXP See description of 0_CTL_ACK_RCVD 2_GPIO_RCVD R W CON180 5 Karbon CXP Cyton CXP See description of 0_GPIO_RCVD 2_TRIG_RCVD R W CON180 6 Karbon CXP Cyton CXP See description of 0_TRIG_RCVD 2_CTL_RSP_ FIFO_OVF R W CON180 7 Karbon CXP Cyton CXP See description of 0_CTL_RSP_FIFO_OVF 2_CTL_REQ_ FIFO_OVF R W...

Page 263: ...on CXP See description of 0_IOACK_UNEXPECTED_INT 2_IOACK_ NOMATCH2 R W CON180 14 Karbon CXP Cyton CXP See description of 0_IOACK_NOMATCH2 2_STRM_PKT_ DROP R W CON180 15 Karbon CXP Cyton CXP See description of 0_STRM_PKT_DROP 2_STRM_NOT_ ENOUGH_DAT R W CON180 16 Karbon CXP Cyton CXP See description of 0_STRM_NOT_ENOUGH_DAT 2_STRM_TOO_ MUCH_DAT R W CON180 17 Karbon CXP Cyton CXP See description of 0...

Page 264: ..._CTL_REQ_FIFO_OVF_M 9 2_GPIO_NOMATCH_M 10 2_TRIG_NOMATCH_M 11 2_IOACK_UNKNOWN_TYPE_M 12 2_IOACK_NOMATCH_M 13 2_IOACK_UNEXPECTED_INT_M 14 2_IOACK_NOMATCH2_M 15 2_STRM_PKT_DROP_M 16 2_STRM_NOT_ENOUGH_DAT_M 17 2_STRM_TOO_MUCH_DAT_M 18 2_STRM_BAD_CRC_M 19 2_STRM_OVERFLOW_M 20 2_STRM_CORNER_M 21 2_SERDES_LOST_ALIGN_M 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29...

Page 265: ...Cyton CXP See description of 0_GPIO_ACK_RCVD_M 2_CTL_ACK_ RCVD_M R W CON181 4 Karbon CXP Cyton CXP See description of 0_CTL_ACK_RCVD_M 2_GPIO_RCVD_ M R W CON181 5 Karbon CXP Cyton CXP See description of 0_GPIO_RCVD_M 2_TRIG_RCVD_ M R W CON181 6 Karbon CXP Cyton CXP See description of 0_TRIG_RCVD_M 2_CTL_RSP_ FIFO_OVF_M R W CON181 7 Karbon CXP Cyton CXP See description of 0_CTL_RSP_FIFO_OVF_M 2_CTL...

Page 266: ...escription of 0_IOACK_UNEXPECTED_INT_M 2_IOACK_ NOMATCH2_M R W CON181 14 Karbon CXP Cyton CXP See description of 0_IOACK_NOMATCH2_M 2_STRM_PKT_ DROP_M R W CON181 15 Karbon CXP Cyton CXP See description of 0_STRM_PKT_DROP_M 2_STRM_NOT_ ENOUGH_DAT_ M R W CON181 16 Karbon CXP Cyton CXP See description of 0_STRM_NOT_ENOUGH_DAT_M 2_STRM_TOO_ MUCH_DAT_M R W CON181 17 Karbon CXP Cyton CXP See description...

Page 267: ... 2_CTL_REQ_FIFO_OVF_WP 9 2_GPIO_NOMATCH_WP 10 2_TRIG_NOMATCH_WP 11 2_IOACK_UNKNOWN_TYPE_WP 12 2_IOACK_NOMATCH_WP 13 2_IOACK_UNEXPECTED_INT_WP 14 2_IOACK_NOMATCH2_WP 15 2_STRM_PKT_DROP_WP 16 2_STRM_NOT_ENOUGH_DAT_WP 17 2_STRM_TOO_WPUCH_DAT_WP 18 2_STRM_BAD_CRC_WP 19 2_STRM_OVERFLOW_WP 20 2_STRM_CORNER_WP 21 2_SERDES_LOST_ALIGN_WP 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserv...

Page 268: ...P See description of 0_GPIO_ACK_RCVD_WP 2_CTL_ACK_ RCVD_WP R W CON182 4 Karbon CXP Cyton CXP See description of 0_CTL_ACK_RCVD_WP 2_GPIO_RCVD_ WP R W CON182 5 Karbon CXP Cyton CXP See description of 0_GPIO_RCVD_WP 2_TRIG_RCVD_ WP R W CON182 6 Karbon CXP Cyton CXP See description of 0_TRIG_RCVD_WP 2_CTL_RSP_ FIFO_OVF_WP R W CON182 7 Karbon CXP Cyton CXP See description of 0_CTL_RSP_FIFO_OVF_WP 2_CT...

Page 269: ...description of 0_IOACK_UNEXPECTED_INT_WP 2_IOACK_ NOMATCH2_WP R W CON182 14 Karbon CXP Cyton CXP See description of 0_IOACK_NOMATCH2_WP 2_STRM_PKT_ DROP_WP R W CON182 15 Karbon CXP Cyton CXP See description of 0_STRM_PKT_DROP_WP 2_STRM_NOT_ ENOUGH_DAT_ WP R W CON182 16 Karbon CXP Cyton CXP See description of 0_STRM_NOT_ENOUGH_DAT_WP 2_STRM_TOO_ WPUCH_DAT_ WP R W CON182 17 Karbon CXP Cyton CXP See ...

Page 270: ...8 2_PKT_RCVD_CNT 9 2_PKT_RCVD_CNT 10 2_PKT_RCVD_CNT 11 2_PKT_RCVD_CNT 12 2_PKT_RCVD_CNT 13 2_PKT_RCVD_CNT 14 2_PKT_RCVD_CNT 15 2_PKT_RCVD_CNT 16 2_PKT_GNT_CNT 17 2_PKT_GNT_CNT 18 2_PKT_GNT_CNT 19 2_PKT_GNT_CNT 20 2_PKT_GNT_CNT 21 2_PKT_GNT_CNT 22 2_PKT_GNT_CNT 23 2_PKT_GNT_CNT 24 2_PKT_GNT_CNT 25 2_PKT_GNT_CNT 26 2_PKT_GNT_CNT 27 2_PKT_GNT_CNT 28 2_PKT_GNT_CNT 29 2_PKT_GNT_CNT 30 2_PKT_GNT_CNT 31 ...

Page 271: ...isters CON184 Version A 0 BitFlow Inc CYT 8 121 2_PKT_RCVD_ CNT RO CON184 15 0 Karbon CXP Cyton CXP See description of 0_PKT_RCVD_CNT 2_PKT_GNT_ CNT RO CON184 31 16 Karbon CXP Cyton CXP See description of 0_PKT_GNT_CNT ...

Page 272: ...8 2_PKT_DROP_CNT 9 2_PKT_DROP_CNT 10 2_PKT_DROP_CNT 11 2_PKT_DROP_CNT 12 2_PKT_DROP_CNT 13 2_PKT_DROP_CNT 14 2_PKT_DROP_CNT 15 2_PKT_DROP_CNT 16 2_CRC_ERR_CNT 17 2_CRC_ERR_CNT 18 2_CRC_ERR_CNT 19 2_CRC_ERR_CNT 20 2_CRC_ERR_CNT 21 2_CRC_ERR_CNT 22 2_CRC_ERR_CNT 23 2_CRC_ERR_CNT 24 2_CRC_ERR_CNT 25 2_CRC_ERR_CNT 26 2_CRC_ERR_CNT 27 2_CRC_ERR_CNT 28 2_CRC_ERR_CNT 29 2_CRC_ERR_CNT 30 2_CRC_ERR_CNT 31 ...

Page 273: ...isters CON185 Version A 0 BitFlow Inc CYT 8 123 2_PKT_DROP_ CNT RO CON185 15 0 Karbon CXP Cyton CXP See description of 0_PKT_DROP_CNT 2_CRC_ERR_ CNT RO CON185 31 16 Karbon CXP Cyton CXP See description of 0_CRC_ERR_CNT ...

Page 274: ...ved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 2_CXP_TRIG_ACK_CNT 25 2_CXP_TRIG_ACK_CNT 26 2_CXP_TRIG_ACK_CNT 27 2_CXP_TRIG_ACK_CNT 28 2_CXP_TRIG_ACK_CNT 29 2_CXP_TRIG_ACK_CNT 30 2_CXP_TRIG_ACK_CNT 31 2_CXP_TRIG_ACK_CNT ...

Page 275: ...s CON186 Version A 0 BitFlow Inc CYT 8 125 2_CXP_TRIG_ STATE RO CON186 0 Karbon CXP Cyton CXP See description of 0_CXP_TRIG_STATE 2_CXP_TRIG_ ACK_CNT RO CON186 31 24 Karbon CXP Cyton CXP See description of 0_CXP_TRIG_ACK_CNT ...

Page 276: ...ved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 2_CXP_GPIO_ACK_CNT 25 2_CXP_GPIO_ACK_CNT 26 2_CXP_GPIO_ACK_CNT 27 2_CXP_GPIO_ACK_CNT 28 2_CXP_GPIO_ACK_CNT 29 2_CXP_GPIO_ACK_CNT 30 2_CXP_GPIO_ACK_CNT 31 2_CXP_GPIO_ACK_CNT ...

Page 277: ...s CON187 Version A 0 BitFlow Inc CYT 8 127 2_CXP_GPIO_ STATE RO CON187 0 Karbon CXP Cyton CXP See description of 0_CXP_GPIO_STATE 2_CXP_GPIO_ ACK_CNT RO CON187 31 24 Karbon CXP Cyton CXP See description of 0_CXP_GPIO_ACK_CNT ...

Page 278: ...LINK_SPEED 5 2_LINK_SPEED 6 2_LINK_SPEED 7 2_LINK_SPEED 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 279: ...CXP Subsystem Registers CON190 Version A 0 BitFlow Inc CYT 8 129 2_LINK_SPEED RO CON190 7 0 Karbon CXP Cyton CXP See description of 0_LINK_SPEED ...

Page 280: ...TATE 5 2_SERDES_STATE 6 2_SERDES_STATE 7 Reserved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 2_SERDES_ALIGNED 31 2_SERDERS_SIGNALDETECT ...

Page 281: ...ERDES_ STATE RO CON191 6 0 Karbon CXP Cyton CXP See description of 0_SERDES_STATE 2_SERDES_ ALIGNED RO CON191 30 Karbon CXP Cyton CXP See description of 0_SERDES_ALIGNED 2_SERDERS_ SIGNALDETECT RO CON191 31 Karbon CXP Cyton CXP See description of 0_SERDERS_SIGNALDETECT ...

Page 282: ...ed 4 Reserved 5 Reserved 6 Reserved 7 Reserved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 283: ...gisters CON192 Version A 0 BitFlow Inc CYT 8 133 2_RAW_DATA_ MODE R W CON192 0 Karbon CXP Cyton CXP See description of 0_RAW_DATA_MODE 2_REMOVE_ IDLES R W CON192 1 Karbon CXP Cyton CXP See description of 0_REMOVE_IDLES ...

Page 284: ...E 10 2_SERDES_ERROR_CODE 11 2_SERDES_ERROR_CODE 12 2_SERDES_ERROR_CODE 13 2_SERDES_ERROR_CODE 14 2_SERDES_ERROR_CODE 15 2_SERDES_ERROR_CODE 16 2_SERDES_ERROR_CODE 17 2_SERDES_ERROR_CODE 18 2_SERDES_ERROR_CODE 19 2_SERDES_ERROR_CODE 20 2_SERDES_ERROR_CODE 21 2_SERDES_ERROR_CODE 22 2_SERDES_ERROR_CODE 23 2_SERDES_ERROR_CODE 24 2_SERDES_ERROR_CODE 25 2_SERDES_ERROR_CODE 26 2_SERDES_ERROR_CODE 27 2_SE...

Page 285: ...CXP Subsystem Registers CON195 Version A 0 BitFlow Inc CYT 8 135 2_SERDES_ ERROR_CODE RO CON195 30 0 Karbon CXP Cyton CXP See description of 0_SERDES_ERROR_CODE ...

Page 286: ...XP_UNDER_LATCH 10 3_POCXP_24V_OK 11 Reserved 12 3_POCXP_STATE 13 3_POCXP_OVR_AUTO_RESTART 14 3_POCXP_SENSE_BYPASS 15 3_ENABLE_POCXP_SYSTEM 16 3_POCXP_CURRENT_LATCH 17 3_POCXP_CURRENT_LATCH 18 3_POCXP_CURRENT_LATCH 19 3_POCXP_CURRENT_LATCH 20 3_POCXP_CURRENT_LATCH 21 3_POCXP_CURRENT_LATCH 22 3_POCXP_CURRENT_LATCH 23 3_POCXP_CURRENT_LATCH 24 3_POCXP_CURRENT 25 3_POCXP_CURRENT 26 3_POCXP_CURRENT 27 3...

Page 287: ...ion of 0_POCXP_CAM_IS_POCXP 3_POCXP_ SHORT_ DETECTED RO CON200 4 Karbon CXP Cyton CXP See description of 0_POCXP_SHORT_DETECTED 3_POCXP_ OPEN_ DETECTED RO CON200 5 Karbon CXP Cyton CXP See description of 0_POCXP_OPEN_DETECTED 3_POCXP_ OVER_ DETECTED RO CON200 6 Karbon CXP Cyton CXP See description of 0_POCXP_OVER_DETECTED 3_POCXP_ OVER_LATCH RO CON200 7 Karbon CXP Cyton CXP See description of 0_PO...

Page 288: ...00 13 Karbon CXP Cyton CXP See description of 0_POCXP_OVR_AUTO_RESTART 3_POCXP_ SENSE_BYPASS RW CON200 14 Karbon CXP Cyton CXP See description of 0_POCXP_SENSE_BYPASS 3_ENABLE_ POCXP_SYSTEM RW CON200 15 Karbon CXP Cyton CXP See description of 0_ENABLE_POCXP_SYSTEM 3_POCXP_ CURRENT_ LATCH RO CON200 23 16 Karbon CXP Cyton CXP See description of 0_POCXP_CURRENT_LATCH 3_POCXP_ CURRENT RO CON200 31 24 ...

Page 289: ..._TIMER 10 3_POCXP_OVER_TIMER 11 3_POCXP_OVER_TIMER 12 3_POCXP_OVER_TIMER 13 3_POCXP_OVER_TIMER 14 3_POCXP_OVER_TIMER 15 3_POCXP_OVER_TIMER 16 3_POCXP_OVER_TIMER 17 3_POCXP_OVER_TIMER 18 3_POCXP_OVER_TIMER 19 3_POCXP_OVER_TIMER 20 3_POCXP_OVER_TIMER 21 3_POCXP_OVER_TIMER 22 3_POCXP_OVER_TIMER 23 3_POCXP_OVER_TIMER 24 3_POCXP_OVER_TIMER 25 3_POCXP_OVER_TIMER 26 3_POCXP_OVER_TIMER 27 3_POCXP_OVER_TIM...

Page 290: ...CON201 The Cyton CXP CYT 8 140 BitFlow Inc Version A 0 3_POCXP_ OVER_TIMER R W CON201 31 0 Karbon CXP Cyton CXP See description of 0_POCXP_OVER_TIMER ...

Page 291: ... 10 3_POCXP_UNDER_TIMER 11 3_POCXP_UNDER_TIMER 12 3_POCXP_UNDER_TIMER 13 3_POCXP_UNDER_TIMER 14 3_POCXP_UNDER_TIMER 15 3_POCXP_UNDER_TIMER 16 3_POCXP_UNDER_TIMER 17 3_POCXP_UNDER_TIMER 18 3_POCXP_UNDER_TIMER 19 3_POCXP_UNDER_TIMER 20 3_POCXP_UNDER_TIMER 21 3_POCXP_UNDER_TIMER 22 3_POCXP_UNDER_TIMER 23 3_POCXP_UNDER_TIMER 24 3_POCXP_UNDER_TIMER 25 3_POCXP_UNDER_TIMER 26 3_POCXP_UNDER_TIMER 27 3_POC...

Page 292: ...CON202 The Cyton CXP CYT 8 142 BitFlow Inc Version A 0 3_POCXP_ UNDER_TIMER R W CON202 31 0 Karbon CXP Cyton CXP See description of 0_POCXP_UNDER_TIMER ...

Page 293: ...M_RCV_FIFO_SIZE 11 3_COM_RCV_FIFO_SIZE 12 3_COM_RCV_FIFO_SIZE 13 3_COM_RCV_FIFO_SIZE 14 3_COM_RCV_FIFO_SIZE 15 3_COM_RCV_FIFO_SIZE 16 3_COM_SEND_FIFO_SIZE 17 3_COM_SEND_FIFO_SIZE 18 3_COM_SEND_FIFO_SIZE 19 3_COM_SEND_FIFO_SIZE 20 3_COM_SEND_FIFO_SIZE 21 3_COM_SEND_FIFO_SIZE 22 3_COM_SEND_FIFO_SIZE 23 3_COM_SEND_FIFO_SIZE 24 3_COM_SEND_FIFO_SIZE 25 3_COM_SEND_FIFO_SIZE 26 3_COM_SEND_FIFO_SIZE 27 3_...

Page 294: ... 8 144 BitFlow Inc Version A 0 3_COM_RCV_ FIFO_SIZE RO CON203 15 0 Karbon CXP Cyton CXP See description of 0_COM_RCV_FIFO_SIZE 3_COM_SEND_ FIFO_SIZE RO CON203 31 16 Karbon CXP Cyton CXP See description of 0_COM_SEND_FIFO_SIZE ...

Page 295: ...1 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 3_COM_SEND_FIFO_CNT 17 3_COM_SEND_FIFO_CNT 18 3_COM_SEND_FIFO_CNT 19 3_COM_SEND_FIFO_CNT 20 3_COM_SEND_FIFO_CNT 21 3_COM_SEND_FIFO_CNT 22 3_COM_SEND_FIFO_CNT 23 3_COM_SEND_FIFO_CNT 24 3_COM_SEND_FIFO_CNT 25 3_COM_SEND_FIFO_CNT 26 3_COM_SEND_FIFO_CNT 27 3_COM_SEND_FIFO_CNT 28 3_COM_SEND_FIFO_CNT 29 3_COM_SEND_FIFO_CNT 30 3_COM_SEND_FIFO_...

Page 296: ...END_ FIFO_CLR WO CON204 0 Karbon CXP Cyton CXP See description of 0_COM_SEND_FIFO_CLR 3_COM_SEND_ GO WO CON204 1 Karbon CXP Cyton CXP See description of 0_COM_SEND_GO 3_COM_SEND_ FIFO_CNT RO CON204 31 16 Karbon CXP Cyton CXP See description of 0_COM_SEND_FIFO_CNT ...

Page 297: ...D_DATA 9 3_COM_SEND_DATA 10 3_COM_SEND_DATA 11 3_COM_SEND_DATA 12 3_COM_SEND_DATA 13 3_COM_SEND_DATA 14 3_COM_SEND_DATA 15 3_COM_SEND_DATA 16 3_COM_SEND_DATA 17 3_COM_SEND_DATA 18 3_COM_SEND_DATA 19 3_COM_SEND_DATA 20 3_COM_SEND_DATA 21 3_COM_SEND_DATA 22 3_COM_SEND_DATA 23 3_COM_SEND_DATA 24 3_COM_SEND_DATA 25 3_COM_SEND_DATA 26 3_COM_SEND_DATA 27 3_COM_SEND_DATA 28 3_COM_SEND_DATA 29 3_COM_SEND_...

Page 298: ...CON205 The Cyton CXP CYT 8 148 BitFlow Inc Version A 0 3_COM_SEND_ DATA R W CON205 31 0 Karbon CXP Cyton CXP See description of 0_COM_SEND_DATA ...

Page 299: ...ved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 3_COM_RCV_FIFO_CNT 17 3_COM_RCV_FIFO_CNT 18 3_COM_RCV_FIFO_CNT 19 3_COM_RCV_FIFO_CNT 20 3_COM_RCV_FIFO_CNT 21 3_COM_RCV_FIFO_CNT 22 3_COM_RCV_FIFO_CNT 23 3_COM_RCV_FIFO_CNT 24 3_COM_RCV_FIFO_CNT 25 3_COM_RCV_FIFO_CNT 26 3_COM_RCV_FIFO_CNT 27 3_COM_RCV_FIFO_CNT 28 3_COM_RCV_FIFO_CNT 29 3_COM_RCV_FIFO_CNT 30 3_COM_RCV_FIFO_CNT 31 3_C...

Page 300: ...P CYT 8 150 BitFlow Inc Version A 0 3_COM_RCV_ FIFO_CLR WO CON206 0 Karbon CXP Cyton CXP See description of 0_COM_RCV_FIFO_CLR 3_COM_RCV_ FIFO_CNT RO CON206 31 16 Karbon CXP Cyton CXP See description of 0_COM_RCV_FIFO_CNT ...

Page 301: ..._COM_RCV_DATA 9 3_COM_RCV_DATA 10 3_COM_RCV_DATA 11 3_COM_RCV_DATA 12 3_COM_RCV_DATA 13 3_COM_RCV_DATA 14 3_COM_RCV_DATA 15 3_COM_RCV_DATA 16 3_COM_RCV_DATA 17 3_COM_RCV_DATA 18 3_COM_RCV_DATA 19 3_COM_RCV_DATA 20 3_COM_RCV_DATA 21 3_COM_RCV_DATA 22 3_COM_RCV_DATA 23 3_COM_RCV_DATA 24 3_COM_RCV_DATA 25 3_COM_RCV_DATA 26 3_COM_RCV_DATA 27 3_COM_RCV_DATA 28 3_COM_RCV_DATA 29 3_COM_RCV_DATA 30 3_COM_...

Page 302: ...CON207 The Cyton CXP CYT 8 152 BitFlow Inc Version A 0 3_COM_RCV_ DATA RO CON207 31 0 Karbon CXP Cyton CXP See description of 0_COM_RCV_DATA ...

Page 303: ...eserved 4 Reserved 5 Reserved 6 Reserved 7 Reserved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 304: ...CON211 The Cyton CXP CYT 8 154 BitFlow Inc Version A 0 3_LINK_INT_ DEST R W CON211 1 0 Karbon CXP Cyton CXP See description of 0_LINK_INT_DEST ...

Page 305: ...IFO_OVF 8 3_CTL_REQ_FIFO_OVF 9 3_GPIO_NOMATCH 10 3_TRIG_NOMATCH 11 3_IOACK_UNKNOWN_TYPE 12 3_IOACK_NOMATCH 13 3_IOACK_UNEXPECTED_INT 14 3_IOACK_NOMATCH2 15 3_STRM_PKT_DROP 16 3_STRM_NOT_ENOUGH_DAT 17 3_STRM_TOO_MUCH_DAT 18 3_STRM_BAD_CRC 19 3_STRM_OVERFLOW 20 3_STRM_CORNER 21 3_SERDES_LOST_ALIGN 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Rese...

Page 306: ...P Cyton CXP See description of 0_GPIO_ACK_RCVD 3_CTL_ACK_ RCVD R W CON212 4 Karbon CXP Cyton CXP See description of 0_CTL_ACK_RCVD 3_GPIO_RCVD R W CON212 5 Karbon CXP Cyton CXP See description of 0_GPIO_RCVD 3_TRIG_RCVD R W CON212 6 Karbon CXP Cyton CXP See description of 0_TRIG_RCVD 3_CTL_RSP_ FIFO_OVF R W CON212 7 Karbon CXP Cyton CXP See description of 0_CTL_RSP_FIFO_OVF 3_CTL_REQ_ FIFO_OVF R W...

Page 307: ...on CXP See description of 0_IOACK_UNEXPECTED_INT 3_IOACK_ NOMATCH2 R W CON212 14 Karbon CXP Cyton CXP See description of 0_IOACK_NOMATCH2 3_STRM_PKT_ DROP R W CON212 15 Karbon CXP Cyton CXP See description of 0_STRM_PKT_DROP 3_STRM_NOT_ ENOUGH_DAT R W CON212 16 Karbon CXP Cyton CXP See description of 0_STRM_NOT_ENOUGH_DAT 3_STRM_TOO_ MUCH_DAT R W CON212 17 Karbon CXP Cyton CXP See description of 0...

Page 308: ..._CTL_REQ_FIFO_OVF_M 9 3_GPIO_NOMATCH_M 10 3_TRIG_NOMATCH_M 11 3_IOACK_UNKNOWN_TYPE_M 12 3_IOACK_NOMATCH_M 13 3_IOACK_UNEXPECTED_INT_M 14 3_IOACK_NOMATCH2_M 15 3_STRM_PKT_DROP_M 16 3_STRM_NOT_ENOUGH_DAT_M 17 3_STRM_TOO_MUCH_DAT_M 18 3_STRM_BAD_CRC_M 19 3_STRM_OVERFLOW_M 20 3_STRM_CORNER_M 21 3_SERDES_LOST_ALIGN_M 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29...

Page 309: ...Cyton CXP See description of 0_GPIO_ACK_RCVD_M 3_CTL_ACK_ RCVD_M R W CON213 4 Karbon CXP Cyton CXP See description of 0_CTL_ACK_RCVD_M 3_GPIO_RCVD_ M R W CON213 5 Karbon CXP Cyton CXP See description of 0_GPIO_RCVD_M 3_TRIG_RCVD_ M R W CON213 6 Karbon CXP Cyton CXP See description of 0_TRIG_RCVD_M 3_CTL_RSP_ FIFO_OVF_M R W CON213 7 Karbon CXP Cyton CXP See description of 0_CTL_RSP_FIFO_OVF_M 3_CTL...

Page 310: ...escription of 0_IOACK_UNEXPECTED_INT_M 3_IOACK_ NOMATCH2_M R W CON213 14 Karbon CXP Cyton CXP See description of 0_IOACK_NOMATCH2_M 3_STRM_PKT_ DROP_M R W CON213 15 Karbon CXP Cyton CXP See description of 0_STRM_PKT_DROP_M 3_STRM_NOT_ ENOUGH_DAT_ M R W CON213 16 Karbon CXP Cyton CXP See description of 0_STRM_NOT_ENOUGH_DAT_M 3_STRM_TOO_ MUCH_DAT_M R W CON213 17 Karbon CXP Cyton CXP See description...

Page 311: ... 3_CTL_REQ_FIFO_OVF_WP 9 3_GPIO_NOMATCH_WP 10 3_TRIG_NOMATCH_WP 11 3_IOACK_UNKNOWN_TYPE_WP 12 3_IOACK_NOMATCH_WP 13 3_IOACK_UNEXPECTED_INT_WP 14 3_IOACK_NOMATCH2_WP 15 3_STRM_PKT_DROP_WP 16 3_STRM_NOT_ENOUGH_DAT_WP 17 3_STRM_TOO_WPUCH_DAT_WP 18 3_STRM_BAD_CRC_WP 19 3_STRM_OVERFLOW_WP 20 3_STRM_CORNER_WP 21 3_SERDES_LOST_ALIGN_WP 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserv...

Page 312: ...P See description of 0_GPIO_ACK_RCVD_WP 3_CTL_ACK_ RCVD_WP R W CON214 4 Karbon CXP Cyton CXP See description of 0_CTL_ACK_RCVD_WP 3_GPIO_RCVD_ WP R W CON214 5 Karbon CXP Cyton CXP See description of 0_GPIO_RCVD_WP 3_TRIG_RCVD_ WP R W CON214 6 Karbon CXP Cyton CXP See description of 0_TRIG_RCVD_WP 3_CTL_RSP_ FIFO_OVF_WP R W CON214 7 Karbon CXP Cyton CXP See description of 0_CTL_RSP_FIFO_OVF_WP 3_CT...

Page 313: ...description of 0_IOACK_UNEXPECTED_INT_WP 3_IOACK_ NOMATCH2_WP R W CON214 14 Karbon CXP Cyton CXP See description of 0_IOACK_NOMATCH2_WP 3_STRM_PKT_ DROP_WP R W CON214 15 Karbon CXP Cyton CXP See description of 0_STRM_PKT_DROP_WP 3_STRM_NOT_ ENOUGH_DAT_ WP R W CON214 16 Karbon CXP Cyton CXP See description of 0_STRM_NOT_ENOUGH_DAT_WP 3_STRM_TOO_ WPUCH_DAT_ WP R W CON214 17 Karbon CXP Cyton CXP See ...

Page 314: ...8 3_PKT_RCVD_CNT 9 3_PKT_RCVD_CNT 10 3_PKT_RCVD_CNT 11 3_PKT_RCVD_CNT 12 3_PKT_RCVD_CNT 13 3_PKT_RCVD_CNT 14 3_PKT_RCVD_CNT 15 3_PKT_RCVD_CNT 16 3_PKT_GNT_CNT 17 3_PKT_GNT_CNT 18 3_PKT_GNT_CNT 19 3_PKT_GNT_CNT 20 3_PKT_GNT_CNT 21 3_PKT_GNT_CNT 22 3_PKT_GNT_CNT 23 3_PKT_GNT_CNT 24 3_PKT_GNT_CNT 25 3_PKT_GNT_CNT 26 3_PKT_GNT_CNT 27 3_PKT_GNT_CNT 28 3_PKT_GNT_CNT 29 3_PKT_GNT_CNT 30 3_PKT_GNT_CNT 31 ...

Page 315: ...isters CON216 Version A 0 BitFlow Inc CYT 8 165 3_PKT_RCVD_ CNT RO CON216 15 0 Karbon CXP Cyton CXP See description of 0_PKT_RCVD_CNT 3_PKT_GNT_ CNT RO CON216 31 16 Karbon CXP Cyton CXP See description of 0_PKT_GNT_CNT ...

Page 316: ...8 3_PKT_DROP_CNT 9 3_PKT_DROP_CNT 10 3_PKT_DROP_CNT 11 3_PKT_DROP_CNT 12 3_PKT_DROP_CNT 13 3_PKT_DROP_CNT 14 3_PKT_DROP_CNT 15 3_PKT_DROP_CNT 16 3_CRC_ERR_CNT 17 3_CRC_ERR_CNT 18 3_CRC_ERR_CNT 19 3_CRC_ERR_CNT 20 3_CRC_ERR_CNT 21 3_CRC_ERR_CNT 22 3_CRC_ERR_CNT 23 3_CRC_ERR_CNT 24 3_CRC_ERR_CNT 25 3_CRC_ERR_CNT 26 3_CRC_ERR_CNT 27 3_CRC_ERR_CNT 28 3_CRC_ERR_CNT 29 3_CRC_ERR_CNT 30 3_CRC_ERR_CNT 31 ...

Page 317: ...isters CON217 Version A 0 BitFlow Inc CYT 8 167 3_PKT_DROP_ CNT RO CON217 15 0 Karbon CXP Cyton CXP See description of 0_PKT_DROP_CNT 3_CRC_ERR_ CNT RO CON217 31 16 Karbon CXP Cyton CXP See description of 0_CRC_ERR_CNT ...

Page 318: ...ved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 3_CXP_TRIG_ACK_CNT 25 3_CXP_TRIG_ACK_CNT 26 3_CXP_TRIG_ACK_CNT 27 3_CXP_TRIG_ACK_CNT 28 3_CXP_TRIG_ACK_CNT 29 3_CXP_TRIG_ACK_CNT 30 3_CXP_TRIG_ACK_CNT 31 3_CXP_TRIG_ACK_CNT ...

Page 319: ...s CON218 Version A 0 BitFlow Inc CYT 8 169 3_CXP_TRIG_ STATE RO CON218 0 Karbon CXP Cyton CXP See description of 0_CXP_TRIG_STATE 3_CXP_TRIG_ ACK_CNT RO CON218 31 24 Karbon CXP Cyton CXP See description of 0_CXP_TRIG_ACK_CNT ...

Page 320: ...ved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 3_CXP_GPIO_ACK_CNT 25 3_CXP_GPIO_ACK_CNT 26 3_CXP_GPIO_ACK_CNT 27 3_CXP_GPIO_ACK_CNT 28 3_CXP_GPIO_ACK_CNT 29 3_CXP_GPIO_ACK_CNT 30 3_CXP_GPIO_ACK_CNT 31 3_CXP_GPIO_ACK_CNT ...

Page 321: ...s CON219 Version A 0 BitFlow Inc CYT 8 171 3_CXP_GPIO_ STATE RO CON219 0 Karbon CXP Cyton CXP See description of 0_CXP_GPIO_STATE 3_CXP_GPIO_ ACK_CNT RO CON219 31 24 Karbon CXP Cyton CXP See description of 0_CXP_GPIO_ACK_CNT ...

Page 322: ...LINK_SPEED 5 3_LINK_SPEED 6 3_LINK_SPEED 7 3_LINK_SPEED 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 323: ...CXP Subsystem Registers CON222 Version A 0 BitFlow Inc CYT 8 173 3_LINK_SPEED RO CON222 7 0 Karbon CXP Cyton CXP See description of 0_LINK_SPEED ...

Page 324: ...TATE 5 3_SERDES_STATE 6 3_SERDES_STATE 7 Reserved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 3_SERDES_ALIGNED 31 3_SERDERS_SIGNALDETECT ...

Page 325: ...ERDES_ STATE RO CON223 6 0 Karbon CXP Cyton CXP See description of 0_SERDES_STATE 3_SERDES_ ALIGNED RO CON223 30 Karbon CXP Cyton CXP See description of 0_SERDES_ALIGNED 3_SERDERS_ SIGNALDETECT RO CON223 31 Karbon CXP Cyton CXP See description of 0_SERDERS_SIGNALDETECT ...

Page 326: ...ed 4 Reserved 5 Reserved 6 Reserved 7 Reserved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 327: ...gisters CON224 Version A 0 BitFlow Inc CYT 8 177 3_RAW_DATA_ MODE R W CON224 0 Karbon CXP Cyton CXP See description of 0_RAW_DATA_MODE 3_REMOVE_ IDLES R W CON224 1 Karbon CXP Cyton CXP See description of 0_REMOVE_IDLES ...

Page 328: ...E 10 3_SERDES_ERROR_CODE 11 3_SERDES_ERROR_CODE 12 3_SERDES_ERROR_CODE 13 3_SERDES_ERROR_CODE 14 3_SERDES_ERROR_CODE 15 3_SERDES_ERROR_CODE 16 3_SERDES_ERROR_CODE 17 3_SERDES_ERROR_CODE 18 3_SERDES_ERROR_CODE 19 3_SERDES_ERROR_CODE 20 3_SERDES_ERROR_CODE 21 3_SERDES_ERROR_CODE 22 3_SERDES_ERROR_CODE 23 3_SERDES_ERROR_CODE 24 3_SERDES_ERROR_CODE 25 3_SERDES_ERROR_CODE 26 3_SERDES_ERROR_CODE 27 3_SE...

Page 329: ...CXP Subsystem Registers CON227 Version A 0 BitFlow Inc CYT 8 179 3_SERDES_ ERROR_CODE RO CON227 30 0 Karbon CXP Cyton CXP See description of 0_SERDES_ERROR_CODE ...

Page 330: ...AR 8 FW_BUILD_YEAR 9 FW_BUILD_YEAR 10 FW_BUILD_YEAR 11 FW_BUILD_YEAR 12 FW_BUILD_YEAR 13 FW_BUILD_YEAR 14 FW_BUILD_YEAR 15 Reserved 16 FW_BUILD_DAY 17 FW_BUILD_DAY 18 FW_BUILD_DAY 19 FW_BUILD_DAY 20 FW_BUILD_DAY 21 FW_BUILD_DAY 22 FW_BUILD_DAY 23 FW_BUILD_DAY 24 FW_BUILD_MONTH 25 FW_BUILD_MONTH 26 FW_BUILD_MONTH 27 FW_BUILD_MONTH 28 FW_BUILD_MONTH 29 FW_BUILD_MONTH 30 FW_BUILD_MONTH 31 FW_BUILD_MO...

Page 331: ...s firmware was compiled in BCD format Example 0x2012 is year 2012 FW_BUILD_DAY RO CON356 23 16 Karbon CXP Cyton CXP Day that this firmware was compiled in BCD format Example 0x18 the 18th of the month FW_BUILD_ MONTH RO CON356 31 24 Karbon CXP Cyton CXP Month that this firmware was compiled in BCD format Example 0x12 is december ...

Page 332: ...D_MIN 6 FW_BUILD_MIN 7 FW_BUILD_MIN 8 FW_BUILD_HOUR 9 FW_BUILD_HOUR 10 FW_BUILD_HOUR 11 FW_BUILD_HOUR 12 FW_BUILD_HOUR 13 FW_BUILD_HOUR 14 FW_BUILD_HOUR 15 FW_BUILD_HOUR 16 FPGA_ID 17 FPGA_ID 18 FPGA_ID 19 FPGA_ID 20 FPGA_ID 21 FPGA_ID 22 FPGA_ID 23 FPGA_ID 24 FW_CMPTBL 25 FW_CMPTBL 26 FW_CMPTBL 27 FW_CMPTBL 28 FW_CMPTBL 29 FW_CMPTBL 30 FW_CMPTBL 31 FW_CMPTBL ...

Page 333: ...led Example 0x35 is 35 minutes past the hour FW_BUILD_ HOUR RO CON357 15 8 Karbon CXP Cyton CXP Hour that this firmware was compiled Example 0x23 is 11pm 23rd hour FPGA_ID RO CON357 23 16 Karbon CXP Cyton CXP FPGA Identifier FW_CMPTBL RO CON357 31 24 Karbon CXP Cyton CXP Firmware compatibility version must match SDK driver internal firmware version ...

Page 334: ...eserved 5 Reserved 6 Reserved 7 Reserved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 335: ...ubsystem Registers CON358 Version A 0 BitFlow Inc CYT 8 185 PFG_RESET R W CON358 0 Karbon CXP Cyton CXP Reset the pfg Stream assembler This register does not get cleared automatically Software must clear it ...

Page 336: ...eserved 4 Reserved 5 Reserved 6 Reserved 7 Reserved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 337: ...0 BitFlow Inc CYT 8 187 NUM_LINKS_ NEEDED R W CON360 2 0 Karbon CXP Cyton CXP Number of active CXP links that a Stream assembler will be working with The LINK_ ORDER register should be configured prior to setting NUM_LINKS to a non zero value ...

Page 338: ...K_1_ORDER 6 LINK_1_ORDER 7 LINK_1_ORDER 8 LINK_2_ORDER 9 LINK_2_ORDER 10 LINK_2_ORDER 11 LINK_2_ORDER 12 LINK_3_ORDER 13 LINK_3_ORDER 14 LINK_3_ORDER 15 LINK_3_ORDER 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 339: ...m decoder will accept packets from NUM_LINKS register determines how many of these physical links will be considered in arbitration LINK_2_ORDER R W CON361 11 8 Karbon CXP Cyton CXP Third physical link that the stream decoder will accept packets from NUM_LINKS reg ister determines how many of these physical links will be considered in arbitration LINK_3_ORDER R W CON361 15 12 Karbon CXP Cyton CXP ...

Page 340: ...P_OUT_TABLE_ODD 6 CXP_OUT_TABLE_ODD 7 CXP_OUT_TABLE_ODD 8 CXP_OUT_TABLE_LPC 9 CXP_OUT_TABLE_LPC 10 CXP_OUT_TABLE_LPC 11 CXP_OUT_TABLE_LPC 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 CXP_OUT_TABLE_EN ...

Page 341: ...d receive the even lines CXP_OUT_ TABLE_ODD R W CON363 7 4 Karbon CXP Selects which VFG should receive the odd lines CXP_OUT_ TABLE_LPC R W CON363 11 8 Karbon CXP Number of lines to send to an odd or even VFG channel before switching CXP_OUT_ TABLE_EN R W CON363 31 Karbon CXP Enable the forwarding of video data to the DMA engines VFGs ...

Page 342: ...PKT_GNT_CNT 9 PKT_GNT_CNT 10 PKT_GNT_CNT 11 PKT_GNT_CNT 12 PKT_GNT_CNT 13 PKT_GNT_CNT 14 PKT_GNT_CNT 15 PKT_GNT_CNT 16 NEXT_LINK 17 NEXT_LINK 18 NEXT_LINK 19 DISABLE_PKT_TAG_CHK 20 UNEXP_PKT_TAG_CNT 21 UNEXP_PKT_TAG_CNT 22 UNEXP_PKT_TAG_CNT 23 UNEXP_PKT_TAG_CNT 24 UNEXP_PKT_TAG_CNT 25 UNEXP_PKT_TAG_CNT 26 UNEXP_PKT_TAG_CNT 27 UNEXP_PKT_TAG_CNT 28 Reserved 29 Reserved 30 Reserved 31 ACTIVE ...

Page 343: ...EXT_LINK RO CON372 18 16 Karbon CXP Cyton CXP The next link from which a packet is expected DISABLE_PKT_ TAG_CHK RO CON372 19 Karbon CXP Cyton CXP Disable the checking of packet tags UNEXP_PKT_ TAG_CNT RO CON372 27 20 Karbon CXP Cyton CXP Number of unexpected packet tags received These are out of order tags The counter wraps and is for debug only ACTIVE RO CON372 31 Karbon CXP Cyton CXP The stream...

Page 344: ...TATE 5 STRM_DECODE_STATE 6 STRM_DECODE_STATE 7 Reserved 8 SOF_ERR 9 SOL_ERR 10 IH_ERR 11 SRC_TAG_ERR 12 IS_LINE_SCAN 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 22 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved ...

Page 345: ...ll be DMAed packed STRM_DECODE_ STATE RO CON428 6 4 Cyton CXP Current state CXP stream decode engine SOF_ERR RO CON428 8 Cyton CXP Bad Start Of Frame Packet SOL_ERR RO CON428 9 Cyton CXP Bad Start Of Line Packet IH_ERR RO CON428 10 Cyton CXP Bad Image Header SRC_TAG_ERR RO CON428 11 Cyton CXP Unexpected Source Tag error IS_LINE_SCAN RO CON428 12 Cyton CXP Camera is a line scan camera ...

Page 346: ...CON428 The Cyton CXP CYT 8 196 BitFlow Inc Version A 0 ...

Page 347: ...terfacing Chapter 9 9 1 Introduction This chapter describes the electrical interface of the Karbon Neon R64 This includes detailed information on the all if the input and output signals In addition information is provided on recommend circuits to use when connecting to these signals ...

Page 348: ...ed triggers will have no effect on the board However they can be used as general purpose inputs 9 2 2 The Optocoupled Trigger The opto coupled trigger allows the acquisition circuitry to accept a trigger signal without having a galvanic connection to the trigger source This is mandatory in some medical and industrial application The trigger information is passed as a light pulse from an on board L...

Page 349: ...l Interfacing Trigger Version A 0 BitFlow Inc CYT 9 3 Figure 9 1 Driver Circuit for Opto Coupled Trigger 220 SFH6325 TRIGGER_OPTO_A TRIGGER_OPTO Frame Grabber User Circuit TRIGGER_OPTO_K 7407 Opto Coupler 5V 5V ...

Page 350: ...ect on the board However they can be used as general purpose inputs 9 3 2 The Optocoupled Encoder The opto coupled encoder allows the acquisition circuitry to accept an encoder sig nal without having a galvanic connection to the encoder source This is mandatory in some medical and industrial application The encoder information is passed as a light pulse from an on board LED that is coupled to a re...

Page 351: ...l Interfacing Encoder Version A 0 BitFlow Inc CYT 9 5 Figure 9 2 Driver Circuit for Opto Coupled Encoder 220 SFH6325 ENCODER_OPTO_A ENCODER_OPTO Frame Grabber User Circuit ENCODER_OPTO_K 7407 Opto Coupler 5V 5V ...

Page 352: ...s These are enumerated in the following sections 9 4 2 R64 GPIN Configuration The R64 has five general purpose inputs The signal level on each input can be read on the corresponding GPIN bit The electrical characteristic of these inputs is shown in the following list GPIN0 GPIN1 Single ended TTL level inputs GPIN2 GPIN3 GPIN4 Differential LVDS inputs 9 4 3 Neon CL GPIN Configuration The Neon CL ha...

Page 353: ...ated GPIN input signals However the status of all inputs can be read at any time This means that any unused inputs can be used a GPIN type signals For example if you are not using the Encoder B TTL input you can read its state at any time using the registers RD_ENCB_TTL This same principle applies to all the all the trigger and encoder inputs A B ...

Page 354: ...pe of GPOUTs The spec ifications for each family are described later in this section 9 5 2 GPOUT Source Options CL Only The source for each GPOUT bit is controlled by the corresponding GPOUTx_CON bit field These are located in CON8 The source for each GPOUT can be programmed independently of the others Table 9 1 shows the sources for each GPOUT 9 5 3 R64 GPOUT Configuration The R64 and R64e model ...

Page 355: ...CL GPOUT Configuration The Karbon CL model boards have seven general purpose outputs However they are divided up between up to four Virtual Frame Grabbers VFGs The electrical char acteristic of these outputs on each VFG are not the same Also different models offer different options Table 9 2 Table 9 3 and Table 9 4 show the options for each model for each VFG Table 9 2 Karbon CL2 F GPOUTs vs VFGs ...

Page 356: ...in two different ways The circuit can be used to drive a opto coupled circuit see Figure 9 3 default configuration or the circuit can be used to drive and opto coupled circuit with galvanic isolation see Figure 9 4 Jumpers are used to configure the driver circuits See the Mechanical chapter on where and how the jumpers are used Table 9 4 Karbon CL4 D GPOUTs vs VFGs Signal VFG0 VFG1 VFG2 VFG3 GPOUT...

Page 357: ...he open collector GPOUT in the factory configuration can drive an opto coupling device The user must supply the 5V to this LED and the two systems must have their grounds connected In this configuration the board and the user s system must have a common electrical ground GPOUT JP3 JP2 12V 5V 5V GPOUT_VCC GPOUT5_OC GND 7407 1K 220 680 User Circuit Opto Coupler 1 2 3 Frame Grabber ...

Page 358: ... the user s LED is supplied by the board s 5V through a 220 Ohm resistor This is achieved by inserting the short in position 1 2 at JP1 The jumper at JP2 is removed The open collector driver will sink the current from the LED There is no gal vanic connection between the board and the user s circuit Information is passed from the board to the user as light transmitted by the LED and received by the...

Page 359: ...r each CC is controlled by the corresponding CCx_CON bitfield Table 9 5 illus trates the source for each CCx as a function of its associated CCx_CON bitfield Table 9 5 CCx_CON CCx_CON CCx Source 0 000b CT0 from CTAB 1 001b CT1 from CTAB 2 010b CT2 from CTAB 3 011b Free running on board signal generator Controlled by FREE_RUN_RATE and FREE_ RUN_HIGH 4 100b Internally generated clock Frequency set b...

Page 360: ...Camera Link Controls CCs The Cyton CXP CYT 9 14 BitFlow Inc Version A 0 ...

Page 361: ...ctors on the board and pin outs for these connectors The mechanical layout of the Cyton CXP4 board is shown in Figure 10 1 Figure 10 1 Cyton CXP4 Board Layout C1 C2 P4 S1 S2 D1 D2 D3 D4 D5 D6 D7 D8 D12 D14 Pin 1 Pin 2 B1 End Vie Pin 59 Pin 60 CTX C1 C2 C3 C4 P5 P4 P1 SW3 1 SW3 2 SW3 3 SW3 4 SW1 2 PCI Express x8 Gen 2 Connector D1 D2 D3 D4 D5 D6 D7 D8 D9 D14 D11 D15 D16 D18 Pin 1 Pin 2 SW2 End View...

Page 362: ... compatible push pull lock and release connectors These con nectors offer many advantage over the BNC connectors they use less space they can handle higher speeds and they have better RF characteristics These connectors are fully compliant with the CoaXPress version 1 1 and later specification Table 10 1 illustrates how to connect the Cyton CXP4 to various types and numbers of CoaxPress Cameras Al...

Page 363: ...in the SW bitfield There is one micro switch block SW3 on the Cyton CXP with four switches These used to control the flash bank that the system boots from Note Do not change these switches unless instructed by BitFlow support See Table 10 3 below which shows the switch settings and the corresponding firm ware bank Table 10 2 Switch S1 Setting SW1 1 SW1 2 SW register down down 0 down up 1 up down 2...

Page 364: ...itches The Cyton CXP CYT 10 4 BitFlow Inc Version A 0 on on off off Reserved on on off on Reserved on on on off Reserved on on on on Reserved Table 10 3 Switch S3 Setting SW3 4 SW3 2 SW 3 2 SW 3 1 FW Bank ...

Page 365: ...ral purpose see register LED_RED D3 Orange General purpose see register LED_ORANGE D4 Green General purpose see register LED_GREEN D5 Green Selectable VFG0 Status see register SEL_LED D6 Green Selectable VFG1 Status see register SEL_LED D7 Green Selectable VFG2 Status see register SEL_LED D8 Green Selectable VFG3 Status see register SEL_LED D9 Green FPGA Configured D11 Various High speed uplink st...

Page 366: ...aning of each color and blink mode is described in Table 10 6 Table 10 5 Downlink LED meaning Color State Meaning Blue Blinking Power sense checking for link that needs power power is not yet applied Blue Steady Power applied turns off after 1 second Green Steady Link established idles being received Green Blinking Packets being received Red Blinking Packet has CRC error Table 10 6 Uplink LED mean...

Page 367: ...ral purpose button SW2 that can be routed to many differ ent destinations The purpose of the button is primarily to help debug I O problems It can be used as a trigger encoder or I O that is routed off the board Please see Sec tion 2 1 for more information on how the button can be routed ...

Page 368: ... Connector P4 For cameras that require more power than can be provide by the PCIe bus the Cyton CXP has a connector P4 which can take auxiliary power from the PC s power supply The pin out for this connector is shown in Table 10 7 Table 10 7 Auxiliary Power Connector Pin Voltage 1 TBD 2 TBD 3 TBD 4 TBD ...

Page 369: ...e I O Box Connector P1 Version A 0 BitFlow Inc CYT 10 9 10 7 The I O Box Connector P1 This connector is for a I O break out box the BitFlow will be offering in the future Please contact BitFlow for more information ...

Page 370: ... In VFG0_TRIGGER LVDS 3 In VFG0_ENCODERA LVDS 4 In VFG0_ENCODERA LVDS 5 In VFG0_ENCODERB LVDS 6 In VFG0_ENCODERB LVDS 7 In VFG1_TRIGGER LVDS 8 In VFG1_TRIGGER LVDS 9 In VFG1_ENCODERA LVDS 10 In VFG1_ENCODERA LVDS 11 In VFG1_ENCODERB LVDS 12 In VFG1_ENCODERB LVDS 13 In VFG2_TRIGGER LVDS 14 In VFG2_TRIGGER LVDS 15 In VFG2_ENCODERA LVDS 16 In VFG2_ENCODERA LVDS 17 In VFG2_ENCODERB LVDS 18 In VFG2_ENC...

Page 371: ...TTL TTL 42 In VFG2_ENCODERA_TTL TTL 43 In VFG2_ENCODERB_TTL TTL 44 In VFG3_TRIGGER_TTL TTL 45 In VFG3_ENCODERA_TTL TTL 46 In VFG3_ENCODERB_TTL TTL 47 Reserved 48 Out VFG0_CC3_TTL TTL 49 Out VFG0_CC4_TTL TTL 50 Out VFG0_CC2_TTL TTL 51 Out VFG1_CC3_TTL TTL 52 Out VFG1_CC4_TTL TTL 53 Out VFG1_CC2_TTL TTL 54 Out VFG2_CC3_TTL TTL 55 Out VFG2_CC4_TTL TTL 56 Out VFG2_CC2_TTL TTL 57 Out VFG3_CC3_TTL TTL 5...

Page 372: ...I O Connector Pinout for the Cyton CXP The Cyton CXP CYT 10 12 BitFlow Inc Version A 0 ...

Page 373: ...8 28 0_IOACK_UNKNOWN_TYPE CYT 8 24 0_IOACK_UNKNOWN_TYPE_CM CYT 8 31 0_IOACK_UNKNOWN_TYPE_M CYT 8 28 0_LINK_INT_DEST CYT 8 21 0_LINK_SPEED CYT 8 41 0_OVER_CURRENT CYT 8 23 0_OVER_CURRENT_CM CYT 8 30 0_OVER_CURRENT_M CYT 8 27 0_PKT_DROP_CNT CYT 8 35 0_PKT_GNT_CNT CYT 8 33 0_PKT_RCVD_CNT CYT 8 33 0_POCXP_24V_OK CYT 8 4 CYT 8 50 CYT 8 94 CYT 8 138 0_POCXP_CAM_IS_POCXP CYT 8 3 0_POCXP_CURRENT CYT 8 5 0...

Page 374: ...CH_M CYT 8 72 1_IOACK_NOMATCH2 CYT 8 69 1_IOACK_NOMATCH2_CM CYT 8 75 1_IOACK_NOMATCH2_M CYT 8 72 1_IOACK_UNEXPECTED_INT CYT 8 69 1_IOACK_UNEXPECTED_INT_CM CYT 8 75 1_IOACK_UNEXPECTED_INT_M CYT 8 72 1_IOACK_UNKNOWN_TYPE CYT 8 69 1_IOACK_UNKNOWN_TYPE_CM CYT 8 75 1_IOACK_UNKNOWN_TYPE_M CYT 8 72 1_LINK_INT_DEST CYT 8 66 1_LINK_SPEED CYT 8 85 1_OVER_CURRENT CYT 8 68 1_OVER_CURRENT_CM CYT 8 74 1_OVER_CU...

Page 375: ..._M CYT 8 116 2_IOACK_NOMATCH2 CYT 8 113 2_IOACK_NOMATCH2_CM CYT 8 119 2_IOACK_NOMATCH2_M CYT 8 116 2_IOACK_UNEXPECTED_INT CYT 8 113 2_IOACK_UNEXPECTED_INT_CM CYT 8 119 2_IOACK_UNEXPECTED_INT_M CYT 8 116 2_IOACK_UNKNOWN_TYPE CYT 8 113 2_IOACK_UNKNOWN_TYPE_CM CYT 8 119 2_IOACK_UNKNOWN_TYPE_M CYT 8 116 2_LINK_INT_DEST CYT 8 110 2_LINK_SPEED CYT 8 129 2_OVER_CURRENT CYT 8 112 2_OVER_CURRENT_CM CYT 8 1...

Page 376: ...M CYT 8 160 3_IOACK_NOMATCH2 CYT 8 157 3_IOACK_NOMATCH2_CM CYT 8 163 3_IOACK_NOMATCH2_M CYT 8 160 3_IOACK_UNEXPECTED_INT CYT 8 157 3_IOACK_UNEXPECTED_INT_CM CYT 8 163 3_IOACK_UNEXPECTED_INT_M CYT 8 160 3_IOACK_UNKNOWN_TYPE CYT 8 157 3_IOACK_UNKNOWN_TYPE_CM CYT 8 163 3_IOACK_UNKNOWN_TYPE_M CYT 8 160 3_LINK_INT_DEST CYT 8 154 3_LINK_SPEED CYT 8 173 3_OVER_CURRENT CYT 8 156 3_OVER_CURRENT_CM CYT 8 16...

Page 377: ... Power CYT 1 8 CON104 CYT 8 2 CON105 CYT 8 6 CON106 CYT 8 8 CON107 CYT 8 10 CON108 CYT 8 12 CON109 CYT 8 14 CON110 CYT 8 16 CON111 CYT 8 18 CON115 CYT 8 20 CON116 CYT 8 22 CON117 CYT 8 26 CON118 CYT 8 29 CON120 CYT 8 32 CON121 CYT 8 34 CON122 CYT 8 36 CON123 CYT 8 38 CON126 CYT 8 40 CON127 CYT 8 42 CON128 CYT 8 44 CON131 CYT 8 46 CON136 CYT 8 48 CON137 CYT 8 51 CON138 CYT 8 53 CON139 CYT 8 55 CON1...

Page 378: ...TATUS CYT 3 27 CPLD_MODE CYT 3 12 CPLD_STRAP CYT 3 12 CURR_FETCH_SIZE CYT 3 8 CXP_OUT_TABLE_EN CYT 8 191 CXP_OUT_TABLE_EVEN CYT 8 191 CXP_OUT_TABLE_LPC CYT 8 191 CXP_OUT_TABLE_ODD CYT 8 191 D DISABLE_PKT_FLUSH_TIMER CYT 3 30 DISABLE_PKT_GEN CYT 3 30 DISABLE_PKT_TAG_CHK CYT 8 193 DISABLE_TIMEOUT CYT 3 10 DST_ADDR_ERROR_LSB CYT 3 27 E EN_ENCA CYT 7 8 EN_ENCB CYT 7 8 EN_TRIG CYT 7 8 ENCA_POL CYT 7 18...

Page 379: ... 41 INT_Z_ACQUIRED_WP CYT 2 43 IS_LINE_SCAN CYT 8 195 L LED_GREEN CYT 7 19 LED_ORANGE CYT 7 19 LED_RED CYT 7 19 LINK_0_ORDER CYT 8 189 LINK_1_ORDER CYT 8 189 LINK_2_ORDER CYT 8 189 LINK_3_ORDER CYT 8 189 M MAX_FETCH_SIZE CYT 3 8 MAX_PAYLOAD_PCIE CYT 3 30 MAX_PAYLOAD_USER CYT 3 30 N NEW_FRAME_RESYNC CYT 3 20 NEXT_ADDR_ERROR_LSB CYT 3 27 NEXT_LINK CYT 8 193 NO_QUAD_AVAIL CYT 3 20 NUM_LINKS_NEEDED CY...

Page 380: ..._BOX_OUT_DIF CYT 7 17 SEL_BOX_OUT_OPTO CYT 7 17 SEL_BOX_OUT_TTL CYT 7 17 SEL_CC1 CYT 7 13 SEL_CC2 CYT 7 13 SEL_CC3 CYT 7 16 SEL_CC4 CYT 7 16 SEL_ENCA CYT 7 11 SEL_ENCB CYT 7 12 SEL_LED CYT 7 14 SEL_TRIG CYT 7 11 SF_CON CYT 2 46 SF_DIM CYT 2 44 SF_HEIGHT CYT 2 45 SF_INC_X CYT 2 48 SF_INC_Y CYT 2 48 SF_INC_Z CYT 2 48 SF_INIT_BYTE CYT 2 47 SF_LINE_SCAN CYT 2 47 SF_MODE CYT 2 47 SF_RUN_LEVEL CYT 2 47 ...

Page 381: ...WR_ON_FULL CYT 3 20 X X_ACQ_COUNT CYT 2 35 X_ACQ_COUNT_CLR_MODE CYT 2 35 X_ACQUIRED CYT 2 34 X_OFFS CYT 2 27 X_SIZE CYT 2 27 X_WIN_DIM CYT 2 26 Y Y_ACQ_COUNT CYT 2 33 Y_ACQUIRED CYT 2 32 Y_CLOSE CYT 2 22 Y_CLOSE_TRIG_FUNC CYT 2 22 Y_CLOSE_TRIG_SEL CYT 2 22 Y_OFFS CYT 2 25 Y_OPEN_TRIG_FUNC CYT 2 22 Y_OPEN_TRIG_SEL CYT 2 23 Y_SIZE CYT 2 25 Y_SYNC CYT 2 23 Y_WIN_CON CYT 2 21 Y_WIN_DIM CYT 2 24 Z Z_AC...

Page 382: ...Index BitFlow Inc ...

Page 383: ...Index BitFlow Inc ...

Page 384: ...Index BitFlow Inc ...

Page 385: ...Index BitFlow Inc ...

Page 386: ...Index BitFlow Inc ...

Page 387: ...Index BitFlow Inc ...

Page 388: ...Index BitFlow Inc ...

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