BenQ Q7T3-FP737S, Service Manual

Page: 88 / 140

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FLASH_WE
RMA DDR[0..15]
RMDATA[0
..7]
RMADDR5
RMDATA0 RMADDR7
RMADDR11
RMADDR9
RMADDR10
TXD
RMADDR11
RMDATA7
RMADDR14
RMDATA7
RMDATA2
SDA
SDA
RMADDR5
RMADDR10
RMDATA6
RMADDR2 RMDATA5 RMADDR12
BANK
RMADDR1
RMADDR8
RMADDR1
RMADDR2
RMADDR8
RMDATA1
SCL
RMDATA1
RMDATA3
RMADDR3
RMADDR14
RMDATA3
RMDATA0
RMADDR6
RMADDR15
RMADDR13
ROM_OEn
RMADDR6
RMADDR7
RXD
RMDATA2
RMADDR12
RMDATA6
RMDATA4
RMADDR3
RMDATA4
RMADDR4 RMADDR9
RMADDR13
RMADDR15
RMADDR8
SCL
RMDATA5
RMADDR14
BANK
RMADDR9
RMADDR0
RMADDR0
RMADDR4
FLASH_WE
3.3V_DDDS 3.3V_SDDS
3.3V_RDDS
3.3V_RGB
3.3V_DVI
2.5V_RXPL
TXD
RXD
D EN
D CLK
TCLK
XTAL
3.3V_DVI
D HS
DVS
Res et
+3.3V
+2.5V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+2.5V
+2.5V +3.3V
+3.3V +3.3V
+3.3V +3.3V +3.3V +3.3V
+3.3V
+3.3V
GREEN- P.2
BLUE+ P.2
BLUE- P.2
VS P.2
HS P.2
RED+ P.2
RED- P.2
GREEN+ P.2
BRT_ADJ
BL_ON
DSUB_SCL
DSUB_SDA
LED_ORG
LED_GRN
VOL_ON/OFF
PW_SW
KEY_MENU
I_KEY
KEY_DEC
KEY_INC
VOLUME
DCLK_TTL
DEN_TTL
DVS_TTL
OB7
OB6
OB5
OB4
OB3
OB2
OB1
OB0
OG7
OG6
OG5
OG4
OG3
OG2
OG1
OG0
OR7
OR6
OR5
OR4
OR3
OR2
OR1
OR0
EB7
EB6
EB5
EB4
EB3
EB2
EB1
EB0
EG7
EG6
EG5
EG4
EG3
EG2
EG1
EG0
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
LVDS_EN
KEY_EXIT
LCD_ON
DHS_TTL
Cable-Detect
RXCP P.2
RXCM P.2
RX2P
P.2
RX2M
P.2
RX1P P.2
RX1M P.2
RX0M P.2
RX0P P.2
Title
Size Document Number R e v .
Date: Sheet o f
Project Code
Reviewed By Approved By Prepared By
Model Name
PCB P/N P CB Rev.
Benq Corporation
OEM/ODM Model Name
99.L8372.000-C2-204-004
INTERFACE BOARD
3 5
JAMSON LIU DAVEN WU
48.L8301.S11 S11
ANGEL HU
<Size>
Q7T3-FP767S 99.L8372.001
0
Tuesday, February 11, 2003
NA
ROM_ADDR9
Available for reading from a status register
1
ROM_ADDR7 If using 6-wire host protocol, program this bit to 1
OCM_START
GPIO(22:16) is on "Host Port" pins
x
HOST_PORT_EN
1 = All 48K of ROM is in external ROM
0
Reserved
HOST_PROTOCOL
x
ROM_ADDR8
0 = XTAL and TCLK pins are connected
1
DESCRIPTION
x ROM_ADDR6
1
Available for reading from a status register
NAME
x
0
ADDRESS SET
USER_BITS(4:0)
Determines polarity of HCLK signal
OCM_ROM_CFG(1)
If using 6-wire host protocol, program this bit to 0
USER_BITS(7:5)
ROM_ADDR14
R e set
Circuit
BOOTSTRAP SIGNALS
SCLPOL
ROM_ADDR13
FLASH/ Prom-Jet Socket
ROM_ADDR(4:0)
32-Pin PLCC Socket
ROM_ADDR(12:10)
ROM_ADDR5
OSC_SEL
1 = OCM becomes active after OCM_CLK is stable
Close to respective power Pins Close to respective power Pins
RS232
OPEN OPEN
OPEN
R e set
Circuit
OPEN
OPEN
C49
0.1U
16V K
+ C14
22U
16V
1
2
C50
0.1U
16V K
Q2
2N3906
3
2
1
C21
47P
OPEN
C58
0.1U
16V K
C16
0.1U
16V K
R69 51K
C34
0.1U
16V K
C55
0.1U
16V K
R24
2.7K
R50
10K
+ C40
22U
16V
1
2
C18
0.1U
16V K
C N1
22P OPEN
8
1
7
2
6
3
5
4
RN10
100
1
2
3
4 8
7
6
5
J3
CON_3P_S
1
2
3
R46
10K
R34
10K
R99 4.7K
+ C41
22U
16V
1
2
+ C28
22U
16V
1
2
CN5
22P OPEN
8
1
7
2
6
3
5
4
CN12
22P OPEN
8
1
7
2
6
3
5
4
R N7
100
1
2
3
4 8
7
6
5
R21 0
R33 0
C57
0.1U
16V K
C N2
22P OPEN
8
1
7
2
6
3
5
4
CN10
22P OPEN
8
1
7
2
6
3
5
4
RN3
100
1
2
3
4 8
7
6
5
R40
10K
R70
10K
C51
0.1U
16V K
C54
0.1U
16V K
L1
BEAD
R44
10K
C N8
22P OPEN
8
1
7
2
6
3
5
4
R36 1KF
C25
0.1U
16V K
C15
0.1U
16V K
C36 4.7P J
C31
0.1U
16V K
R35
10K
RN4
100
1
2
3
4 8
7
6
5
C20
0.1U
16V K
L2
BEAD
C53
0.1U
16V K
R47
10K
C39
0.1U
16V K
C26
0.1U
16V K
C30
0.1U
16V K
Int_Test
U4
GM2120
710212000E
RED+
171
RED-
170
GREEN+
167
GREEN-
166
BLUE+
163
BLUE-
162
RX2+
179
RX2-
180
RX1+
185
RX1-
186
RX0+
191
RX0-
192
XTAL
151
TCLK
152
GPIO0/PWM0
40
GPIO1/PWM1
41
GPIO2/PWM2
42
GPIO3/TIMER1
43
GPIO4/UART_D1
44
GPIO5/UART_D0
45
GPIO6/EXTCLK
46
GPIO7
47
GPIO10/TCON_ROE3
49
GPIO11
50
GPIO12
51
GPIO13
52
DCLK/TCON_OCLK
118
DEN/TCON_ECLK
115
DVS/TCON_FSYNC
117
DHS/TCON_LP
116
RXC-
195
RXC+
194
REXT
174
TCON_OPOL
120
TCON_OINV
121
TCON_ESP
122
TCON_EPOL
123
TCON_EINV
124
TCON_RSP2
125
TCON_RSP3
126
TCON_RCLK
127
TCON_ROE
128
GPIO20/HDATA3
206
GPIO19/HDATA2
207
GPIO18/HDATA1
208
GPIO17/HDATA0
1
GPIO16/HFS
205
GPIO22/HCLK
204
RESETn
5
GPIO21/IRQn
4
DDC_SCL
6
DDC_SDA
7
GPIO9/TCON_ROE2
48
GPIO8/IRQINn
39
CLKOUT
201
ROM_ADDR0
25
ROM_ADDR1
24
ROM_ADDR2
23
ROM_ADDR3
22
ROM_ADDR4
19
ROM_ADDR5
18
ROM_ADDR6
17
ROM_ADDR7
16
ROM_ADDR8
15
ROM_ADDR15
8
ROM_DATA0
35
ROM_DATA1
34
ROM_DATA2
33
ROM_DATA3
32
ROM_DATA4
31
ROM_DATA5
30
ROM_DATA6
29
ROM_DATA7
28
ROM_ADDR14
9
ROM_ADDR13
10
ROM_ADDR9
14
ROM_ADDR11
12
ROM_ADDR10
13
ROM_ADDR12
11
ROM_OEn
36
VDD1_ADC_2.5
155
VDD2_ADC_2.5
153
AGND_GREEN
165
AGND_RED
169
AGND_BLUE
161
AGND_ADC
158
SGND_ADC
157
AGND_RX2
178
RVDD
2
RVDD
20
RVDD
53
RVDD
67
RVDD
81
RVDD
97
RVDD
111
RVDD
129
CVDD
26
CVDD
88
CVDD
134
CVDD
203
VDD_RX2_2.5
176
PPWR
113
PBIAS
114
AGND_IMB
175
VDD_RX1_2.5
182
AGND_RX1
184
VDD_RX0_2.5
188
AGND_RX0
190
AGND_RXC
197
AGND_RXPLL
198
VDD_RXPLL_2.5
199
AVDD_RPLL
150
AVSS_RPLL
149
VDD_DPLL_3.3
148
AVDD_SDDS
146
VDD_SDDS_3.3
144
AVDD_DDDS
141
VDD_DDDS_3.3
139
AVSS_SDDS
145
AVSS_DDDS
140
HSYNC
137
VSYNC
136
RVSS
3
RVSS
21
RVSS
38
RVSS
54
RVSS
68
RVSS
82
RVSS
98
RVSS
112
RVSS
130
CVSS
89
CVSS
133
CVSS
202
CVSS
135
GND1_ADC
156
GND2_ADC
154
GND_RX2
177
GND_RX1
183
GND_RX0
189
VSS_DPLL
147
VSS_SDDS
143
VSS_DDDS
138
N/C
200
ADC_TEST
159
PD6/ER6
61
PD7/ER7
62
PD10/EG2
65
PD11/EG3
66
PD12/EG4
69
PD13/EG5
70
PD14/EG6
71
PD15/EG7
72
PD33/OG1
94
PD32/OG0
93
PD18/EB2
75
PD19/EB3
76
PD20/EB4
77
PD21/EB5
78
PD22/EB6
79
PD23/EB7
80
PD17/EB1
74
PD16/EB0
73
PD26/OR2
85
PD27/OR3
86
PD28/OR4
87
PD29/OR5
90
PD30/OR6
91
PD31/OR7
92
PD25/OR1
84
PD24/OR0
83
PD34/OG2
95
PD35/OG3
96
PD36/OG4
99
PD37/OG5
100
PD38/OG6
101
PD39/OG7
102
PD9/EG1
64
PD8/EG0
63
PD42/OB2
105
PD43/OB3
106
PD44/OB4
107
PD45/OB5
108
PD46/OB6
109
PD47/OB7
110
PD41/OB1
104
PD40/OB0
103
TCON_OSP
119
CVSS
27
Reserved
131
N/C
142
Reserved
132
AVDD_IMB
173
AVDD_RX2
181
AVDD_RX1
187
AVDD_RX0
193
AVDD_RXC
196
AVDD_BLUE
164
AVDD_GREEN
168
AVDD_RED
172
AVDD_ADC
160
PD5/ER5
60
PD4/ER4
59
PD3/ER3
58
PD2/ER2
57
PD1/ER1
56
PD0/ER0
55
RVDD
37
C60
0.1U
16V K
R27
10K
R52
10K
C101
1U
10V Z
R N1
100
1
2
3
4
8
7
6
5
U7
AT24C16 16K
NC
1
NC
2
NC
3
GND
4
SDA
5
SCL
6
WP
7
VCC
8
RN11
100
1
2
3
4 8
7
6
5
C52
0.1U
16V K
C38
0.1U
16V K
RN8
100
1
2
3
4 8
7
6
5
C37
0.1U
16V K
R25
10K
C35 4.7P J
R51
10K
R68
10K
RN13
100
1
2
3
4 8
7
6
5
R29
100K
+
C33
22U
16V
1
2
R48
10K
+
C23
22U
16V
1
2
C29
0.1U
16V K
R42
10K
C N3
22P OPEN
8
1
7
2
6
3
5
4
L6
BEAD
R38
10K
U9
V6300L OPEN
NC
1
VSS
2
NC
3
VDD
5
RES
4
R N9
100
1
2
3
4 8
7
6
5
R41
10K
Y1 14.318MHZ
R39
10K
C27
0.1U
16V K
C N6
22P OPEN
8
1
7
2
6
3
5
4
CN11
22P OPEN
8
1
7
2
6
3
5
4
R N5
100
1
2
3
4 8
7
6
5
L4
BEAD
R22
1KF
RN12
100
1
2
3
4 8
7
6
5
R N2
100
1
2
3
4 8
7
6
5
L3
BEAD
R31
3KF
C N4
22P OPEN
8
1
7
2
6
3
5
4
C N9
22P OPEN
8
1
7
2
6
3
5
4
C N7
22P OPEN
8
1
7
2
6
3
5
4
R37
10K U6 SST 39VF010
A15
3
A14
29
A13
28
A12
4
A11
25
A10
23
A9
26
A8
27
A7
5
A6
6
A5
7
A4
8
A3
9
A2
10
A1
11
A0
12
DQ7
21
DQ6
20
DQ5
19
DQ4
18
DQ3
17
DQ2
15
DQ1
14
DQ0
13
OE
24
WE
31
VCC
32
NC
1
GND
16
A16
2
NC/A17
30
CE
22
C32
0.1U
16V K
C59
0.1U
16V K
+ C17
22U
16V
1
2
C19
0.1U
16V K
R43
10K R49
10K
R28
10K
D9
1N4148
1
2
R32 0
R45
10K
C42
0.1U
16V K
RN6
100
1
2
3
4 8
7
6
5
C43
0.1U
16V K
L5
BEAD
C22
47P
OPEN
C44
0.1U
16V K
C56
0.1U
16V K
C45
0.1U
16V K
C46
0.1U
16V K
C47
0.1U
16V K
R26
10K
C48
0.1U
16V K
C24
0.1U
16V K