Operation Manual
EL512.256-H3 Series Display
Beneq Oy
Olarinluoma 9
Tel. +358 9 7599 530
VAT ID FI19563372
FI-02200 Espoo
Fax +358 9 7599 5310
www.beneq.com
Finland
www.lumineq.com
Date: February 13, 2017
Document number: ED000818B
Page | 5
Pins
Signal
Symbol
Description
13
Video Clock
VCLK
The VCLK signal shifts data present on the VID
and TVID lines into the display system. VCLK is
active on the rising edge.
15
Video Data
VID
Signal that supplies the pixel information to the
system.
12, 14,
16
Ground
GND
Signal return.
J2 (Optional power input connector)
1
Voltage
V
cc2
Same as J1, Pins 1, 2 (not necessary to connect if
power is supplied via J1).
2, 3
Ground
GND
Same as J1 Pins 6, 8, 10, 12, 14, 16 (not
necessary to connect if power is supplied via J1).
4
Voltage
V
cc1
Same as J1 Pins 3, 4 (not necessary to connect if
power is supplied via J1).
5
Low Power
_LOWPWR The power consumption of the display is lowered
to the LOWPWR values if the _LOWPWR is low,
internally pulled high if left disconnected.
6
Enable
ENABLE
The operation of the display unit is disabled if the
ENABLE input is low, internally pulled high if left
disconnected.
J3 (Optional control input connector)
1
Luminance
Pot.1
LUMPOT1 Input for external luminance control (see page
8). Can be left disconnected.
2
Luminance
Pot.2
LUMPOT2 Input for external luminance control. Can be left
disconnected.
3, 4
Reserved
Reserved, do not connect.
3.3
Control basics
The TFEL panel has 512 transparent column electrodes crossing 256 row electrodes in an X-Y
fashion. Light is emitted when an AC voltage is applied at a row-column intersection. The
display operation is based on the symmetric, line-at-a-time data addressing scheme, which is
synchronized by the external VS, HS, and VCLK input signals. The internal control signals and
the high voltage pulses for the column and row drivers are generated internally by the control
electronics. All control signal inputs are HCT-compatible with pull-up resistors.
