Operation Manual
EL320.240-FA3 Display
Beneq Oy
Olarinluoma 9
Tel. +358 9 7599 530
VAT ID FI19563372
FI-02200 Espoo
Fax +358 9 7599 5310
www.beneq.com
Finland
www.lumineq.com
Date: February 13, 2017
Document number: ED000813B
Page | 15
Table 3. Logic signal requirements
Description
Min
Max
Units
Notes
Absolute input logic voltage
range
-0.3
5.5
V
For all inputs except V
H
,
LUMA
Logic high voltage
2.0
5.5
V
All input thresholds are TTL
Logic low voltage
-0.3
0.8
V
All input thresholds are TTL
LUMA input voltage
0
5.5
V
Leave open if not used
LUMA input current
-250
0
µA
Note:
1. All logic inputs (except LUMA input) are 5 V tolerant, with 270 Ω series resistors.
2. Input capacitance for all logic inputs except LUMA is 8 pF typical.
3. DE, LUM0, and LUM1 have > 20 kΩ pull-up resistors to 3.3 V.
4. VS, SHUTDOWN, and V/Q have > 20 kΩ pull-down resistors to ground
3.5.4
Video mode timing—SGD video mode
Item
Description
Min.
Max.
Units
1
HS high time
30
ns
2
Last VCLK fall to HS fall
20
ns
3
HS to VCLK rising edge
10
ns
4
R/G data setup to VCLK
10
ns
5
R/G data hold from VCLK
10
ns
6
VCLK period
100
ns
7
VCLK low width
30
ns
8
VCLK high width
30
ns
9
VS high setup to HS low
140
ns
10
VS hold after HS
140
ns
11
VS low setup to HS high
140
ns
12
HS period
34
µs
VS period
240
HS periods
VS frequency
120
Hz
