BENECOM BEM-100B, User Manual

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BEM-100B/C
56 BEM-100B/C User’s Manual
2.3.3 Advanced Chipset Features
2.3.3.1 DRAM Clock/Drive Control
When select to “BySPD”, the DRAM timing parameters are set according to DRAM SPD
(Serial Presence Detect). When disabled, one can manually set the DRAM timing
parameters through the sub items below. Set to “BySPD” if not sure.
2.3.3.2 CAS Latency Time
Controls the latency between the SDRAM Read command and the time data actually
becomes available.
2.3.3.3 DRAM RAS# to CAS# Delay
Controls the latency between the DDR SDRAM active command and the read/write
command.
2.3.3.4 DRAM RAS# Precharge
Controls the idle clocks after issuing a precharge command to the DDRSDRAM.
2.3.3.5 Precharge delay (tRAS)
Precharge Delay This setting controls the precharge delay, which determines the timing
delay for DRAM precharge.