System Overview
Plexus 9000 Planning and Engineering Guide
Issue 6, May 14, 2004
Section 130-110-000
3-20
Telica,
Inc.
P113-AA
09-14-00
REAR VIEW
Ground
Lug
UL 1950
Label
Warning
Label
FCC Rules
Label
Fan Fuse B
Fan Fuse A
Power A
Power B
B
A
B
A
NEG
48Vdc
30 A
RTN
(ESD)
Electrostatic
Discharge
I/O-17
21
FAN FUSE 2A
GND
I/O-16
20
I/O-15
19
I/O-14
18
I/O-13
17
I/O-12
16
I/O-11
15
I/O-10
14
SP/
TMGB
13
SP/
TMGA
9
SW
FABB
12
SW
FABA
10
I/O-9
11
[PROT]
I/O-8
8
I/O-7
7
[PROT]
I/O-6
6
I/O-5
5
I/O-4
4
I/O-3
3
I/O-2
2
I/O-1
1
ESD
Read and understand
operator's manual before
using this machine.
Failure to follow operating
instructions could result
in death or serious injury
WARNING
L I S T E D
R
C
U S
2000811
ETL LISTED
CONFORMS TO
UL STD 1950
CERTIFIED TO
CAN/CSA STD C22.2 NO.950
This device complies with Part 15 of
the FCC Rules. Operation is subject to
the following two conditions: (1) This
device may not cause harmful
interference, and (2) this device must
accept any interference that may
cause undesired operation.
Read and understand
operator's manual before
using this machine.
Failure to follow operating
instructions could result
in death or serious injury
WARNING
L I S T E D
R
C
U S
2000811
ETL LISTED
CONFORMS TO
UL STD 1950
CERTIFIED TO
CAN/CSA STD C22.2 NO.950
SYSTEM
PROCESSOR
TIMING
SYSTEM
PROCESSOR
TIMING
SWITCH
FABRIC
A
SWITCH
FABRIC
B
DS3
I/O
DS3
I/O
DS3
I/O
DS3
I/O
DS3
I/O
DS3
I/O
DS3
I/O
DS3
I/O
DS1
I/O
DS1
I/O
DS1
I/O
DS1
I/O
DS1
I/O
DS1
I/O
DS1
I/O
DS1
I/O
DS3
I/O
Figure 3-8. Plexus 9000 Chassis, Lower Rear View
3.3.2 Common Modules
3.3.2.1 System
Processor
Two SP units, each comprising a front and a rear circuit card, are located
near the center of the shelf (slots 9 and 13) and provide full 1+1
redundancy for critical processing resources for true non-stop operation.
The SP has two redundant six Gb disk drives, one located on each of the
rear cards, which hold the entire switch and circuit provisioning databases.
This strategic location allows for processor replacement without having to
reload the system software in the drive. This in turn ensures that the
system rapidly regains full protection capability once the replacement SP
is inserted. Dual independent signaling and network management
interfaces located on the system processors provide a constant interface to
network management systems and IP signaling networks. The IP
signaling network interface allows multiple Plexus 9000s to be connected
to a common signaling gateway.
The SPs also hold the internal Stratum 3 timing sources. Network timing
is brought into the rear of the unit via two independent connections
interfacing to the central office Building Integrated Timing System
(BITS). Recovered timing from IOM-1 and 2 or IOM-8 and 10 can also
be used. The Plexus 9000 provides complete timing system redundancy
for protection against BITS source, line interface or internal clock failure.
Holdover is provided in the event of a complete loss of BITS timing.