DS3 ATM Network Access Module
Plexus 9000 Planning and Engineering Guide
Issue 1, April 23, 2004
Section 130-120-800
5-200
Telica,
Inc.
5.18.3.1
Line Interface Units (LIUs)
The LIU receives and equalizes the bipolar AMI B3ZS (DS-3) data from
the midplane and the rear module. It retimes the received data and
supplies it to the framer. It detects a loss of signal (LOS), checks for
bipolar violations (BPVs) and decodes it into an NRZ signal for the
framers.
In the transmit direction, the LIU receives AMI data from the framer,
shapes the pulse and sends the data to the midplane and the rear module.
It can also provide a point of loopback and insert an alarm indication
signal (AIS) if required.
5.18.3.2 Framers
The framers receive the AMI T3 signal from the LIUs, provide frame
synchronization and alarm detection, and accumulate line code violations,
framing errors, parity errors, and FEBE events. It hunts for ATM cells
embedded in the payload of the T3 and passes the cells to the APC.
In the transmit direction the framer inserts framing for M23 or C-bit parity
for DS-3 and passes data to LIUs.
5.18.3.3
ATM Port Controller (APC)
The APC maintains and manages the ATM virtual connections (VC).
They perform the scheduling and policing of ATM functions on the data
flowing through the module. The APC connects to the SAR with one
Utopia bus and to the framers on another.
5.18.3.4 Phazit
The Phazit links the APC to the SERDES device. In the transmit
direction, the Phazit switches the active switch fabric ports to the APC,
synchronizes transfers between the SERDES and the APC and checks the
integrity of the data from the midplane.
5.18.3.5 Serializer/Deserializer
(SERDES)
The SERDES provide the data interface to the switch fabric. It takes the
data from the Phazit and embeds the clock and sends the clock/data stream
to the SF module or takes the 1.0 GHz embedded clock/data stream from
the SF and extracts a clock from it and provides data to the Phazit
circuitry.