Plexus 9000 Planning and Engineering Guide
Octal DS3/STS-1 I/O Front Module
Section 130-120-600
Issue 4, March 26, 2004
Telica, Inc.
5-155
5.13.3.4
Maintenance Link Bus Adapter (MLBA) and EEPROM
The Maintenance Link Bus Adapter (MLBA), which has a serialized
point-to-point interconnect between the SF module and each IOM,
controls the Super Mappers on each module. This link is used to reset an
IOM, detect the presence and CLEI code of the rear module, control the
LEDs located on the module, download images to the processor’s
memory, program the circuit switch registers and communicate
operational status from the IOM to the SP.
Each module also has a 256 byte EEPROM of non-volatile memory that
contains the board specific information such as the CLEI code, part
number, serial number and revision number. This information can be
retrieved with the
RTRV-INFO-EQPT
TL1 command.
5.13.3.5
Microprocessor and Memory
Each module has a microprocessor with 512Kbyte of L2 Cache 64 Mbytes
of SDRAM, and 32 Mbytes of non-volatile Flash memory for controlling
the module. The Flash memory contains code that performs initialization,
OS boot, diagnostics, and debug monitor.
The microprocessor has an HDLC (High-level Data Link Control)
Controller. Timeslot 24 of each of the 224 T1s that the module processes
is an HDLC D-channel that must be transferred between the processor and
the TSU and FSU. The HDLC provides the interface.
5.13.3.6
Digital Signal Processor (DSP)
The DSP is on a daughter card (Shown within the dotted lines below the
connector on the block diagram.) of the 89-0411 and 89-0425 modules.
The DSP is used for DTMF digit collection or tone detection. The
daughter card receives its power from the motherboard and regulates it for
card use.
5.13.3.7 Power
Each Octal DS-3/STS-1 I/O front module has its own DC-to-DC converter
(not shown), which converts the 48 volts supplied from the backplane to
the local voltages required (5Vdc, 3Vdc, etc.). The front modules supply
power for the rear modules.
5.13.3.8
Clocks and Synchronization
Clock and framing information is received from the BITS circuitry
because the Maintenance Link, ATM switch fabric and line interfaces all
operate synchronously to the BITS timing supplied to the chassis. The
clock control circuitry of the IOM distributes these on the module.