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Plexus 9000 Planning and Engineering Guide
Triple DS3/STS-1 I/O Front Module
Section 130-120-500
Issue 2, March 26, 2004
Telica, Inc.
5-139
Each module also has a 256 byte EEPROM of non-volatile memory that
contains the board specific information such as the CLEI code, part
number, serial number and revision number. This information can be
retrieved with the
RTRV-INFO-EQPT
TL1 command.
5.11.3.5
Microprocessor and Memory
Each module has a microprocessor with 512Kbyte of L2 Cache 64 Mbytes
of SDRAM, and 32 Mbytes of non-volatile Flash memory for controlling
the module. The Flash memory contains code that performs initialization,
OS boot, diagnostics, and debug monitor.
The microprocessor has an HDLC (High-level Data Link Control) MCC
(Multi-Channel Controller). Timeslot 24 of each of the 84 T1s that the
module processes is an HDLC D-channel that must be transferred between
the processor and the TSU and FSU. The HDLC provides the interface.
5.11.3.6
Digital Signal Processor (DSP)
The DSP is on a daughter card (Shown within the dotted lines below the
connector on the block diagram.) of the 89-0410 and 89-0424 modules.
The DSP is used for DTMF digit collection or tone detection. The
daughter card receives its power from the motherboard and regulates it for
card use.
5.11.3.7 Power
Each Triple DS-3 I/O front module has its own DC-to-DC converter (not
shown), which converts the 48 volts supplied from the backplane to the
local voltages required (5Vdc, 3Vdc, etc.). The front modules supply
power for the rear modules and to the daughter card of the 89-0410 IOM.
5.11.3.8
Clocks and Synchronization
Clock and framing information is received from the BITS circuitry
because the Maintenance Link, ATM switch fabric and line interfaces all
operate synchronously to the BITS timing supplied to the chassis. The
clock control circuitry of the IOM distributes these on the module.
5.11.3.9
DS3/STS-1 Protection Module
I/O-5 (physical slot 5) and I/O-13 (physical slot 17) are the slots for the
DS-3/STS-1 protection module in the 85-3004 or 85-3007 chassis. The T3
protection bus allows the front protection module to transmit/receive T3
signal pairs from rear IOMs. I/O-5 provides protection for I/O-1 to I/O-4
and I/O-6 to I/O-8; I/O-13 provides protection for I/O-9 to I/O-12 and I/O-
14 to I/O-17. This provides N:1 redundancy for electrical interfaces.