BIOS
CB6464
57
Version: 0.4
9.35
PCI Express Root Port X
Bios-Entry
Options
PCI Express Root Port 1
Disabled / Enabled
Topolgy
Unknown / x1 / x4 / Sata Express / M2
ASPM
L0sL1 / L1 L0s / Disabled / Auto
L1 Substates
Disabled / L1.1 & L1.2 / L1.1 / L1.2
Gen3 Eq Phase3 Method
Hardware / Static Coeff. / Software Search
UDTP
0..10
DPTP
0..10
ACS
Disabled / Enabled
URR
Disabled / Enabled
FER
Disabled / Enabled
NFER
Disabled / Enabled
CER
Disabled / Enabled
CTO
Disabled / Enabled
SEFE
Disabled / Enabled
SENFE
Disabled / Enabled
SECE
Disabled / Enabled
PME SCI
Disabled / Enabled
Hot Plug
Disabled / Enabled
Advanced Error Reporting
Disabled / Enabled
PCIe Speed
Auto / Gen1 / Gen2 / Gen3
Transmitter Half Swing
Disabled / Enabled
Detect Timeout
0..65535
Extra Bus Reserved
0..7
Reserved I/O
4K / 8K / 12K / 16K / 20K
PCH PCIe LTR Configuration
PCH PCIE1 LTR
Disabled / Enabled
Snoop Latency Override
Disabled / Manual / Auto
Snoop Latency Value
0..1023
Snoop Latency Multipler
1 ns / 32 ns / 1024 ns / 32768 ns / 1048576 ns / 33554432 ns
Non Snoop Latency Override
Disabled / Manual / Auto
Summary of Contents for CB6464
Page 1: ...Manual for Computerboard CB6464 0 4 25 10 2019 Version Date...
Page 2: ......
Page 6: ...CB6464 6 Version 0 4...
Page 64: ...Mechanical drawings CB6464 64 Version 0 4 10 2 PCB Pin 1 distances Fig 14 MZ Pin1 CB6464_G3...
Page 65: ...Mechanical drawings CB6464 65 Version 0 4 10 3 PCB Dimensions Fig 15 MZ CB6464_G3...
