Annex: Post-Codes
Beckhoff New Automation Technology
CB3052
page 81
Code
Description
93h
Reading in of the hard disk boot sector for the inspection through the internal anti virus program
(trend anti virus code)
94h
1. Enabling of level 2 cache
2. Setting of the clock speed during the boot process
3. Final initialising of the chip set.
4. Final initialising of the power management.
5. Erase the onscreen and display the overview table (rectangular box).
6. Program “write allocation” at K6 CPUs (AMD)
7. Program “write combining” at P6 CPUs (INTEL)
95h
1. Program the changeover of summer-and winter-time
2. Update settings of keyboard-LED and keyboard repeat rates
96h
1. Multi processor system: generate MP-table
2. Generate and update ESCD-table
3. Correct century settings in the CMOS (20xx or 19xx)
4. Synchronise the DOS-system timer with CMOS-time
5. Generate an MSIRQ-Routing table..
C0h
Chip set initialising:
- Cut off shadow RAM
- Cut off L2 cache (apron 7 or older)
- Initialise chip set register
C1h
Memory detection:
Auto detection of DRAM size, type and error correction (ECC or none)
Auto detection of L2 cache size (apron 7 or older)
C3h
Unpacking of the packed BIOS program codes into the random access memory.
C5h
Copying of the BIOS program code into the shadow RAM (segments E000 & F000) via chipset
hook.
CFh
Testing of the CMOS read/write functionality
FFh
Boot trial over boot-loader-routine (software-interrupt INT 19h)
