REF: BBONEBLK_SRM
BeagleBone Black System
Reference Manual
Rev A5.2
Page 52 of 108
Input Data Mask Line:
DM is an input mask signal for write data. Input data is masked
when DM is sampled HIGH along with the input data during a write access. Although the
DM ball is input-only, the DM loading is designed to match that of the DQ and DQS
balls. DM is referenced to VREFDQ.
On-die Termination Line:
ODT enables (registered HIGH) and disables (registered
LOW) termination resistance internal to the DDR3L SDRAM. When enabled in normal
operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and
DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if
disabled via the LOAD MODE command. ODT is referenced to VREFCA.
6.3.3
Power Rails
The
DDR3L
memory device and the DDR3 rails on the processor are supplied by the
TPS65217C
. Default voltage is 1.5V but can be scaled down to 1.35V if desired.
6.3.4
VREF
The
VREF
signal is generated from a voltage divider on the
VDDS_DDR
rail that
powers the processor DDR rail and the DDR3L device itself.
Figure 31
below shows the
configuration of this signal and the connection to the DDR3L memory device and the
processor.
U12
MT41K256M16HA-125
VREF_DQ
H1
VREF_CA
M8
15mm x 15mm
Package
U5A
XAM3359AZCZ
VREFSSTL
J4
C124
0.1uf ,6.3V
R100
10K,1%
R98
10K,1%
C123
0.001uf ,50V
DGND
DDR_VREF
VDDS_DDR
DGND
DGND
C28
0.1uf ,6.3V
DDR_VREF
Figure 31.
DDR3L VREF Design
