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11. Signal Input Selection R763850 & R763851
3. Sync clamping-restoration (sheet 1/12).
HS/CS and VS sync processing
Most of the sync processing, like HS / VS separation is done inside the ADC chip. Hence, the sync signals just need a little restoration
prior to enter them into the AD9888. The negative peak level of the HS and VS pulses are clamped at approximately ground level
with one OPAMP in I2 and then put at the right level and amplitude with another OPAMP in I2. As such they can be applied to the
AD9888 analog-digital converter.
COAST signal (see sheet 2/11, input pin 53 of I4).
In most computer signals, H sync pulses are provided continuously on a separate wire (separate HS). The sequence of the sync
pulses is not interrupted. In some systems however, H sync is disturbed during the V sync period (equalization pulses, Macrovision
pulses, …). In other cases they disappear. To avoid upsetting the clock generator it is important to ignore these distortions. The
COAST signal, generated on the PMP (AMDS section) is an asynchronous input that disables the PLL input and allows the clock to
free-run at its current frequency. The PLL can run several lines without significant drift.
11.3.1.2.2 DVI input (sheet 3/11).
1. Signal flow
The eight RX* signals are routed straight to the SIL161 receiver chip which delivers 3x8x2 bit (three colors, 8-bit and split odd/even
pixels). This is the BUS_RX destined for the DVI Re-syncer I12 (see sheet 4/11). This FPGA must deliver the BUS_TX for the DVI
OUT and the BUS_TO_INPUT for the multiplexer. This signal is in fact put on the same bus of the RGB_ANA1 output of the ADC
(see sheet 5/11). The BUS_TX is converted to the DVI standard with a SIL160.
2. Display resolution info. (DDC lines and Hot Plug detection)
The DVI graphics card in the image generator must generate the DVI signals at the correct native resolution of the display (the
projector in this case). The info required by the DVI source is programmed in the I²C controlled E²PROM I7. The moment the source
is connected the Hot plug detect line activate the switchers Q3-Q4 such that the DDC Clock and DDC DATA lines are connected to
the E³PROM . The DVI source now can read the requested data from this memory. In case of an upgrade of the info, the E²PROM
lines can be connected to the CPU I²C bus SCL_PL and SDA_PL with the PL1_WE line.
The E²PROM receives its power supply from the projector or from the DVI source in case the projector is in stand-by or switched
OFF.
11.3.1.2.3 Analog to digital converter I4 (AD9888KS).
Description
The pixel clock output frequencies of the AD9888 range from 10 to 205MHz and is compatible with the UXGA resolution
(1600x1200@75hz). The ADC generates its own clock based on the HSYNC_1 input or accepts an external clock. RGB or YUV
signals are converted into 48 bits (3 colors, 8-bit depth and odd/even split).
The digital decoder outputs are connected in parallel to the ADC outputs. Therefore, when the ADC is active, the decoder outputs
must be switched to a three-state level. If the decoder is active, the ADC outputs must be three-state.
Finally, the power supply is delivered by an external regulator I20, taking its input from the +5V power line.
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R5976820 SLM R12+ PERFORMER 08/03/2005
Summary of Contents for SLM R12 Plus
Page 1: ...SLM R12 Performer Service Manual R9010170 R9010171 R5976820 00 08 03 2005...
Page 8: ...Table of contents 6 R5976820 SLM R12 PERFORMER 08 03 2005...
Page 12: ...1 Safety 10 R5976820 SLM R12 PERFORMER 08 03 2005...
Page 36: ...5 SLM R12 P Location of the Fans 34 R5976820 SLM R12 PERFORMER 08 03 2005...
Page 56: ...8 Local Keypad LCD Display 54 R5976820 SLM R12 PERFORMER 08 03 2005...
Page 82: ...11 Signal Input Selection R763850 R763851 80 R5976820 SLM R12 PERFORMER 08 03 2005...
Page 90: ...13 Digital Inputs Backplane R763378 88 R5976820 SLM R12 PERFORMER 08 03 2005...
Page 126: ...15 Lamp Power Supply R7633705 124 R5976820 SLM R12 PERFORMER 08 03 2005...
Page 130: ...16 Start Pulse Generator SPG R763512 128 R5976820 SLM R12 PERFORMER 08 03 2005...
Page 168: ...22 Infra Red Receiver Module R763261 166 R5976820 SLM R12 PERFORMER 08 03 2005...
Page 174: ...24 Projector Tilt Switch R764240 172 R5976820 SLM R12 PERFORMER 08 03 2005...
Page 178: ...25 Light Output Sensor R763294 176 R5976820 SLM R12 PERFORMER 08 03 2005...
Page 182: ...26 Lamp Info Module R763295 180 R5976820 SLM R12 PERFORMER 08 03 2005...
Page 258: ...27 Maintenance 256 R5976820 SLM R12 PERFORMER 08 03 2005...
Page 274: ...29 Overview of the Electrical Diagrams 272 R5976820 SLM R12 PERFORMER 08 03 2005...
Page 280: ...Index 278 R5976820 SLM R12 PERFORMER 08 03 2005...