B&R Panel PC 3100, User Manual

Page: 163 / 277

Software
Automation PC 3100 User's manual V 1.00
Translation of the original documentation
163
4.1.7.2.9.1 PCI Express configuration
BIOS parameter Setting options Description
Disabled PCI Express clock gating
Enabled
Disables/Enables PCI Express clock gating for root ports
Disabled Legacy IO low latency
Enabled
Disables/Enables legacy IO low latency
Disabled DMI link ASPM control
Enabled
Disables/Enables DMI link ASPM control
PCIE port assigned to LAN - Displays the PCIe port assigned to the LAN
Disabled Port8xh decode
Enabled
Disables/Enables Port8xh decoding
Disabled Peer memory write enable
Enabled
Disables/Enables peer memory write enable
Disabled Compliance test mode
Enabled
Disables/Enables compliance test mode
Disabled PCIe USB glitch W/A
1)
Enabled
Disables/Enables PCIe USB glitch W/A
For faulty USB devices after the PCIe/PEG
2)
port
Disabled PCIe function swap
Enabled
Disables/Enables PCIe function swap
PCI Express Gen3 eq lanes Enter Opens submenu "PCI Express Gen3 eq lanes" on page 163
PCI Express root port n
3)
Enter Opens submenu "PCI Express root port n" on page 163
Table 189: Advanced - PCH-IO configuration - PCI Express configuration
1) PCIe-USB glitch workaround
2) PCIe for graphics
3) Depending on the hardware, all available PCIe root ports are listed.
PCI Express Gen3 eq lanes
BIOS parameter Setting options Description
PCIE n
1)
Cm INT
Default:
6
Defines PCIE n Cm
Range: 0 to 63
PCIE
n
1)
Cp INT
Default: 2
Defines PCIE
n
Cp
Range: 0 to 63
Disabled Override SW EQ setting
Enabled
Disables/Enables SW EQ setting override
Coeff
q
2)
Cp INT
Default: (Diverse)
Defines
q
Cp
Range: 0 to 63
Coeff q
2)
Cm INT
Default: 2
Defines q Cm
Range: 0 to 63
Table 190: Advanced - PCH-IO configuration - PCI Express configuration - PCI Express Gen3 Eq Lanes
1)
n
is the number of available PCIe root ports.
2) q ranges from 0 to 5.
PCI Express root port n
BIOS parameter Setting options Description
Disabled PCI Express root port n
1)
Enabled
Disables/Enables PCI Express root port n
x4
Unknown
x1
SATA Express Topology
M2
Selects the PCIe root port topology
Auto
Disabled
L0sL1
L0s
ASPM
L1
Selects PCIe Active State Power Management manually/automatically or disables it
Disabled
L1.1
L1.2 L1 substates
L1.1 & L1.2
Selects or disables L1 substates
Hardware
Software search
Gen3 Eq Phase3 Method
Static coeff.
PCIe Gen3 equalization Phase3 method
UPTP
2)
INT
Default:
5
Selects the UPT preset
Range: 0 to 10
DPTP
3)
INT
Default: 7
Selects the DPT preset
Range: 0 to 10
Disabled ACS
4)
Enabled
Disables/Enables access control services extended capabilities
Table 191: Advanced - PCH-IO configuration - PCI Express root port
n
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