X20 system modules • Motor controllers • X20SM1426
1996
X20 system User's Manual 3.10
Position latched sync/async
Name:
PositionLatchedSync
PositionLatchedASync
The position counter (internal position counter or ABR counter) is applied at the latch event (see "Module config-
uration 2"). Bits 3 and 7 of the Counter configuration register are used to determine which counter state (internal
position counter or ABR encoder) should be saved in the registers "Position latched sync" and "Position latched
async".
Data type
Value
INT
-32,768 to 32,767
Counter configuration
Register
Bit 3 … 0
Bit 3 … 1
Position sync
Internal position counter
ABR counter
Position async
ABR counter
Internal position counter
Internal position counter
The internal position counter is the position calculated by the SM module (set position). This is a cyclic 16-bit
counter.
The lowest 5 to 8 bits represent microsteps, while the highest 8 to 11 bits represent full steps (depending on bits
5 and 6 of the register Module configuration 1).
Example of the internal position counter format (7-bit micro steps, i.e. set bit 5 and 6 of the module configuration
to binary 10):
15
0
14 13 12
11 10
9
8
7
6
5
4
3
2
1
0
6
5
4
3
2
1
8
7
6
5
4
3
2
1
0
Full steps
Microsteps
ABR counter
This counter is a cyclic 16-bit counter. The relationship between this counter and the internal position counter
depends on the resolution of the ABR encoder and the microsteps defined for the internal position counter.
usSinceTrigger
Name:
usSinceTrigger
This register indicates the time (in µs) that has passed since the trigger event occurred (see "Module configuration
Data type
Value
UINT
0 to 65,535
Stepper latch trigger status
Name:
LatchInput
LatchDone
TriggerInput
Data type
Value
USINT
See bit structure.
Bit structure:
Bit
Description
Value
Information
0
Latch input:
x
Digital input for the latch event (level)
1
LatchDone
x
State changes each time the counter state is successfully
latched (reset value = 0)
2 - 3
Reserved
-
4
TriggerInput
x
Trigger input (level)
5 - 7
Reserved
0
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