SBC81613 Socket 370 All-in-One CPU Card Series User
’
s Manual
Hardware Description
23
4.7.4 Flat
Panel
Connector Pin Description
LCD1, LCD2 Pin Description
CN11 Pin Description
Name Description
P0~P35
Flat panel data output
ENABKL Activity
Indicator and Enable Backlight
outputs
SHFCLK Shift
clock.
Pixel
clock for flat panel data
M
M signal for panel AC drive control
LP
Latch pulse. Flat panel equivalent of HSYNC
FLM
First line marker. Flat panel equivalent of
VSYNC
+12VM
+12V power controlled by chipset
ENAVEE / ENAVDD Power sequencing controls for panel LCD
bias volt
VDDM
3.3V or 5V selected by
JP9
Name Description
TXU0~3
Channel 1 Data output
TXL0~3
Channel 0 Data output
BLON
Back Light Enable output
DIGON
Indicator Activity output
12V
+12V power controued by chip set
VDDM
3.3V or 5V selected by
JP1
TXUCK
Channel 1 clock output
TXLCK
Channel 0 clock output
