Avnet Xilinx Zynq 7Z045 Manual Download Page 31

Page: 31 / 36

Page 31

BB2 Connector
Signal Name

I/O Connector
Signal Name

JX2
Pin #

7Z045
Pin #

JX2
Pin #

I/O Connector
Signal Name

BB2 Connector
Signal Name

JTAG_TCK

MMP_JTAG_TCK

Y12

V10

MMP_JTAG_TMS

JTAG_TMS

PB0

JX2_SE_IO_0_P

Y30

AA30

JX2_SE_IO_0_N

PB1

PB2

JX2_SE_IO_2_P

Y28

AA29

JX2_SE_IO_2_N

PB3

SFP0_TX_FAULT_VT JX2_SE_IO_4_P

AG26

AG27

JX2_SE_IO_4_N

SFP0_TX_DISABLE

SFP0_MOD2_VT

JX2_SE_IO_6_P

AF29

AG29

JX2_SE_IO_6_N

SFP0_MOD1

SFP0_MOD0_VT

JX2_SE_IO_8_P

Y26

Y27

JX2_SE_IO_8_N

SFP0_RSEL

SFP0_LOS_VT

JX2_SE_IO_10_P

AE25

AF25

JX2_SE_IO_10_N

PMOD1_P1_VT

PMOD1_P2_VT

JX2_SE_IO_12_P

AA27

AA28

JX2_SE_IO_12_N

PMOD1_P3_VT

PMOD1_P4_VT

JX2_SE_IO_14_P

AC26

AD26

JX2_SE_IO_14_N

PMOD1_P7_VT

PMOD1_P8_VT

JX2_SE_IO_16_P

AD30

AE30

JX2_SE_IO_16_N

PMOD1_P9_VT

FMC_VADJ

JX2_VCCIO_SE

FMC_VADJ

PMOD1_P10_VT

JX2_SE_IO_18_P

AC29

AD29

JX2_SE_IO_18_N

PMOD2_P1_VT

PMOD2_P2_VT

JX2_SE_IO_20_P

AF30

AG30

JX2_SE_IO_20_N

PMOD2_P3_VT

PMOD2_P4_VT

JX2_SE_IO_22_P

AE28

AF28

JX2_SE_IO_22_N

PMOD2_P7_VT

PMOD2_P8_VT

JX2_SE_IO_24_P

AB27

AC27

JX2_SE_IO_24_N

PMOD2_P9_VT

PMOD2_P10_VT

JX2_SE_IO_26_P

AE27

AF27

JX2_SE_IO_26_N

SD1_D0_VT

SD1_D1_VT

JX2_SE_IO_28_P

AB29

AB30

JX2_SE_IO_28_N

SD1_D2_VT

SD1_D3_VT

JX2_SE_IO_30_P

AD25

AE26

JX2_SE_IO_30_N

SD1_CMD

SD1_CLK

JX2_SE_IO_32_P

AH28

MMP_CONF_ PROGRAM FPGA_PROG#

CDCE_Y2_OUT

JX2_SE_CLK

AC28

JX2_Vref_SE

GND

PCIe-RX2_P

JX2_MGTRX0_P

JX2_MGTTX0_P

PCIe-TX2_P

PCIe-RX2_N

JX2_MGTRX0_N

JX2_MGTTX0_N

PCIe-TX2_N

GND

PCIe-RX3_P

JX2_MGTRX1_P

JX2_MGTTX1_P

PCIe-TX3_P

PCIe-RX3_N

JX2_MGTRX1_N

JX2_MGTTX1_N

PCIe-TX3_N

GND

PCIe-RX0_P

JX2_MGTRX2_P

JX2_MGTTX2_P

PCIe-TX0_P

PCIe-RX0_N

JX2_MGTRX2_N

JX2_MGTTX2_N

PCIe-TX0_N

GND

PCIe-RX1_P

JX2_MGTRX3_P

JX2_MGTTX3_P

PCIe-TX1_P

PCIe-RX1_N

JX2_MGTRX3_N

JX2_MGTTX3_N

PCIe-TX1_N

GND

LJ-PCIe-REFCLK0_P JX2_MGTREFCLK_P

MGTAVTT (1.2 V)

1V2

LJ-PCIe-REFCLK0_N JX2_MGTREFCLK_N

MGTAVTT (1.2 V)

1V2

1V0

MGTAVCC (1.0V)

MGTAVCC (1.0 V)

1V0

MGTAVCC (1.0V)

MGTAVCC (1.0 V)

1V0

FMC1-LA15_P

JX2_DIFF_IO_0_P

V28

U25

JX2_DIFF_IO_1_P

FMC1-LA16_P

FMC1-LA15_N

JX2_DIFF_IO_0_N

V29

V26

JX2_DIFF_IO_1_N

FMC1-LA16_N

Summary of Contents for Xilinx Zynq 7Z045

Page 1: ...c AVNET Reach Further and the AV logo are registered trademarks of Avnet Inc All other brands are the property of their respective owners LIT 5151 GSG AES 7Z7045 G 01 V1 Xilinx Zynq 7Z045 Mini Module Plus Development Kit Version 1 0 ...

Page 2: ...Page 2 Document Control Document Version 1 0 Document Date 8 28 2013 Revision History Version Date Comment 1 0 8 28 2013 Initial release for production board AES MMP 7Z045 G Revision B ...

Page 3: ... Your own internal testing evaluation and design efforts at a single Customer site c make use and sell the Product in a single production unit No other rights are granted and Avnet and any other Product licensor reserves all rights not speciﬁcally granted in this License Agreement Except as expressly permitted in this License neither the Design Kit Documentation nor any portion may be reverse engi...

Page 4: ...y rights of Avnet and any third parties No other governments are authorized to use the Product without written agreement of Avnet and applicable third parties 9 Ownership Licensee acknowledges and agrees that Avnet or Avnet s licensors are the sole and exclusive owner of all Intellectual Property Rights in the Licensed Materials and Licensee shall acquire no right title or interest in the Licensed...

Page 5: ...ace 19 2 3 4 I2 C EEPROM Interface 20 2 3 5 Micro SD Card Interface 20 2 4 Clock Sources 21 2 4 1 CDCM61001 Programmable LVDS Clock Synthesizer 22 2 5 Communication 24 2 5 1 10 100 1000 Ethernet PHY 24 2 5 2 USB UART 25 2 5 3 USB 2 0 On the Go OTG 25 2 6 Real Time Clock RTC 26 2 7 Power on Reset 26 2 8 Configuration 27 2 8 1 Configuration Modes and Boot Settings 27 2 8 2 JTAG Interface PL TAP and ...

Page 6: ...le Plus Development Board 12 Figure 4 PCI Express x4 Interface 13 Figure 5 DDR3 SDRAMInterface 16 Figure 6 Parallel Flash Interface 18 Figure 7 7Z045 QSPI Flash Interface 20 Figure 8 Clock Nets Connected to Global Clock Inputs 21 Figure 9 CDCM61001 Clock Synthesizer 22 Figure 10 10 100 1000 Ethernet Interface 24 Figure 11 JTAG Interface 28 Figure 12 Power Supply Diagram 33 Figure 13 Board Jumpers ...

Page 7: ... Pin Assignments 19 Table 8 I2 C EEPROM Pin Assignments 20 Table 9 CDCM61001 Clock Synthesizer Pin Description 23 Table 10 CDCM61001 Common Application Settings 23 Table 11 Ethernet PHY Pin Assignments 25 Table 12 USB UART Pin Assignments 25 Table 13 USB 2 0 Pin Assignments 26 Table 14 RTC Pin Assignments 26 Table 15 Setting the Configuration Mode SW5 27 Table 16 PJTAG Pin Assignments 28 Table 17 ...

Page 8: ... Z7045 Mini Module Plus is compatible with one Avnet designed baseboard Avnet Designed Baseboard Avnet Orderable Part Number Mini Module Plus Baseboard 2 AES MMP BB2 G 1 2 Board Features 1 3 Reference Designs Reference designs that demonstrate some of the potential applications of the Zynq Z7045 Mini Module Plus Development Kit can be downloaded from the Avnet Design Resource Center www em avnet c...

Page 9: ...nformation The following table lists the development kit part number Internet link at www em avnet com MMP 7Z045 G Part Number Hardware AES MMP 7Z045 G Xilinx Zynq 7Z045 Mini Module Plus Development Kit populated with an XC7Z045 FFG900 1 speed grade device Table 1 Ordering Information ...

Page 10: ...scription A high level block diagram of the Zynq 7Z045 Mini Module Plus development board is shown below followed by a brief description of each sub section Figure 2 Zynq 7Z045 Mini Module Plus Development Board Block Diagram ...

Page 11: ...nt Gen2 x8 Analog Mixed Signal 2x 12 bit MSPS ADCs with up to 17 differential inputs Security AES SHA 256b Table 2 Zynq 7Z045 AP SoC Features 2 2 GTX Interface The GTX transceiver is a full duplex serial transceiver for point to point transmission applications Up to 16 transceivers are available on a single 7Z045 FFG900 device The transceiver block is designed to operate at up to 12 5 Gb s per cha...

Page 12: ...nk has reference clock inputs One of these reference clock inputs are supplied by on board clock sources while two others are supplied from the baseboard A single programmable LVDS synthesizer is used to provide variable frequency clock sources to GTX bank 109 This synthesizer provides reference clock frequencies that support the full range of line rates The following figure shows the clock source...

Page 13: ...e Xilinx website for more details The PCI Express electrical interface on the Zynq 7Z045 Mini Module Plus Development Board consists of 4 lanes having unidirectional transmit and receive differential pairs It supports second generation PCI Express data rates of 5 0 Gbps In addition to the data lanes there is a 100 MHz reference clock that is provided from the system slot In order to work in open s...

Page 14: ...iguration Timing The Zynq 7Z045 Mini Module Plus Development Board meets the 200 ms configuration time requirement for ATX based PC systems when configuring from the QSPI interface 2 2 3 GTX for FMC Expansion Connector SFP Display Port and SMA Baseboard Four other high speed gigabit interfaces from the Mini Module Plus Baseboard 2 are connected to the 7Z045 via the JX1 connector Each interface is ...

Page 15: ...upport various types of applications Each development board has five memory interfaces 1 DDR3 1GB x32 DDR3 SDRAM 2 32 MB QSPI Flash 3 256 MB Parallel Flash x16 4 8 KB I2 C EEPROM 5 SD Micro Card 2 3 1 DDR3 SDRAM Interface Two Micron DDR3 SDRAM devices part number MT41K256M16HA 125E E make up the 1 GB x32 SDRAM memory interface Each device provides 512 MB of memory on a single IC and is organized a...

Page 16: ...nd reference voltage is 0 75 V The following guidelines were used in the design of the DDR3 interface to the 7Z045 These guidelines are based on Micron recommendations and board level simulation DDR3 devices routed with daisy chain topology for shared signals of the two devices clock address control 40 ohm controlled trace impedance for single ended signals 80 ohm differential impedance for differ...

Page 17: ...E28 DDR3_D20 E30 DDR3_D21 F28 DDR3_D22 G30 DDR3_D23 F30 DDR3_D24 J29 DDR3_D25 K27 DDR3_D26 J30 DDR3_D27 J28 DDR3_D28 K30 DDR3_D29 M29 DDR3_D30 L30 DDR3_D31 M30 DDR3_DM1 B30 DDR3_DM2 H29 DDR3_DM3 K28 DDR3_CS N22 Net Name 7Z045 Pin DDR3_A0 L25 DDR3_A1 K26 DDR3_A2 L27 DDR3_A3 G25 DDR3_A4 J26 DDR3_A5 G24 DDR3_A6 H26 DDR3_A7 K22 DDR3_A8 F27 DDR3_A9 J23 DDR3_A10 G26 DDR3_A11 H24 DDR3_A12 K23 DDR3_A13 H2...

Page 18: ... PC28F device is an asynchronous memory that also supports a synchronous burst read mode for high performance applications The PC28F device has a 100 nanosecond access time The PC28F flash connects to Bank 34 of the 7Z045 The Flash I O voltage is 1 8 V The following figure shows the PC28F flash interface on the development board Figure 6 Parallel Flash Interface ...

Page 19: ...ration time requirement Net Name 7Z045 Pin PFLASH_D0 L12 PFLASH_D1 H12 PFLASH_D2 L10 PFLASH_D3 K12 PFLASH_D4 J11 PFLASH_D5 K10 PFLASH_D6 J10 PFLASH_D7 K7 PFLASH_D8 G10 PFLASH_D9 H11 PFLASH_D10 L9 PFLASH_D11 L8 PFLASH_D12 H7 PFLASH_D13 L7 PFLASH_D14 J8 PFLASH_D15 G9 PFLASH_CE B10 PFLASH_WE J9 PFLASH_OE H8 PFLASH_RST E7 PFLASH_ADV G7 PFLASH_WAIT H9 PFLASH_CLK K11 Net Name 7Z045 Pin PFLASH_A1 A9 PFLA...

Page 20: ...EEPROM for additional data storage A Micron M24C08 R is the device used The I2 C EEPROM is on the shared I2 C bus with the I2 C real time clock RTC The table below shows the pin connections to the 7Z045 Table 8 I2 C EEPROM Pin Assignments 2 3 5 Micro SD Card Interface The Zynq 7Z045 Mini Module Plus Development Board implements a micro SD card interface that can be used for boot configuration as w...

Page 21: ... on board LVDS clock synthesizer All of these clocks are tied to the Z7045 MRCC pins giving access to the 7Z045 s global clock tree The clock sources described in this section are used to derive the required clocks for the memory and communications devices and the general system clocks for the logic design For a description of the GTX reference clock sources see Section 2 2 1 The following figure ...

Page 22: ... Zynq 7Z045 Mini Module Plus Development Board design uses the TI CDCM61001 LVDS frequency synthesizer for generating various clock frequencies as an input reference clock for GTX bank 109 A list of features included in the CDCM61001 device is shown below Output frequency range 43 75 MHz to 683 264 MHz RMS period jitter 0 509 ps 625 MHz Output rise and fall time 255 ps maximum Output duty cycle va...

Page 23: ...der values The CDCM61001 FD and OD values are programmed via dipswitches SW3 and SW4 These dipswitches should be configured prior to powering up the board The following table shows how to set the dipswitches for a common application All the values are based on a 25 MHz crystal clock input to the CDCM61001 device Interconnect Technology OUT0 and OUT1 MHZ PR1 PR0 OD2 OD1 OD0 SATA 150 0 0 0 1 1 GigE ...

Page 24: ... The PHY device is a Marvel 88E1518 The PHY is connected to a Tyco Electronics RJ 45 jack with integrated magnetics part number 1840808 7 The jack also integrates two LEDs that indicate a valid link and traffic over the interface The PHY clock is generated from a 25 MHz crystal The following figure shows a high level block diagram of the interface to the Ethernet PHY Figure 10 10 100 1000 Ethernet...

Page 25: ...ctrostatic discharge when plugging in a USB cable Two jumpers allow the switching of device modes from OTG Host mode or endpoint mode The USB 2 0 circuit ships in endpoint mode by default To switch the device into OTG mode JP11 must be moved to the 2 3 position and JP7 must be placed The USB3320 device also offers over current detection protection when in OTG mode U16 provide the 7Z045 with an OC ...

Page 26: ...a power on reset IC and circuit to insure the 7Z045 PS_POR and PS_SRST signals de assert in the correct sequence at power up To accomplish this the Maxim MAX16025TE device is used and is referenced on the board as U8 As shipped the delay sequence is programmed to release the PS_SRST signal before the PS_POR signal The delay for PS_POR Is adjustable and set by C66 which as shipped is a 3300pf capac...

Page 27: ...endent mode only the PL system is included While in independent mode the ARM DAP is accessible but the user must use a separate JTAG cable via the 20 pin PJTAG connector J5 SW5 position 4 controls the PLL The following table shows the two configuration modes and settings and the proper SW5 position settings Table 15 Setting the Configuration Mode SW5 2 8 2 JTAG Interface PL TAP and ARM DAP The Zyn...

Page 28: ...jumpers NOTE JP10 must be placed in either position to allow the 7Z045 PS Block to come out of reset If no jumper is placed the 7Z045 will be non functional By default this jumper is populated in position 2 3 2 8 3 PJTAG Interface ARM DAP The Zynq 7Z045 Mini Module Plus Development Board has a dedicated JTAG connector that can be used to debug trace the PS ARM processor via third party debugger tr...

Page 29: ... 4 JX1_SE_IO_0_N FMC1 LA29_N FMC1 LA31_P JX1_SE_IO_2_P 5 AH18 AJ18 6 JX1_SE_IO_2_N FMC1 LA31_N FMC1 LA30_P JX1_SE_IO_4_P 7 AG17 AG16 8 JX1_SE_IO_4_N FMC1 LA30_N FMC1 LA33_P JX1_SE_IO_6_P 9 AE12 AF12 10 JX1_SE_IO_6_N FMC1 LA33_N FMC1 LA32_P JX1_SE_IO_8_P 11 AE16 AE15 12 JX1_SE_IO_8_N FMC1 LA32_N SDA_0_VT JX1_SE_IO_10_P 13 AE13 AF13 14 JX1_SE_IO_10_N SCL_0 FMC_TRST_L JX1_SE_IO_12_P 15 AE18 AE17 16 J...

Page 30: ...1_DIFF_IO_4_P 87 AJ20 AJ23 88 JX1_DIFF_IO_5_P FMC1 LA06_P FMC1 LA05_N JX1_DIFF_IO_4_N 89 AK20 AJ24 90 JX1_DIFF_IO_5_N FMC1 LA06_N 1V5 1 5V 91 92 1 5 V 1V5 FMC1 LA07_P JX1_DIFF_IO_6_P 93 AJ21 AH23 94 JX1_DIFF_IO_7_P FMC1 LA08_P FMC1 LA07_N JX1_DIFF_IO_6_N 95 AK21 AH24 96 JX1_DIFF_IO_7_N FMC1 LA08_N 1V0 VCCINT 97 98 VCCINT 1V0 FMC1 LA11_P JX1_DIFF_IO_8_P 99 AD21 AJ25 100 JX1_DIFF_IO_9_P FMC1 LA12_P ...

Page 31: ...27 AC27 30 JX2_SE_IO_24_N PMOD2_P9_VT PMOD2_P10_VT JX2_SE_IO_26_P 31 AE27 AF27 32 JX2_SE_IO_26_N SD1_D0_VT SD1_D1_VT JX2_SE_IO_28_P 33 AB29 AB30 34 JX2_SE_IO_28_N SD1_D2_VT SD1_D3_VT JX2_SE_IO_30_P 35 AD25 AE26 36 JX2_SE_IO_30_N SD1_CMD SD1_CLK JX2_SE_IO_32_P 37 AH28 Y9 38 MMP_CONF_PROGRAM FPGA_PROG CDCE_Y2_OUT JX2_SE_CLK 39 AC28 40 JX2_Vref_SE NC GND GND 41 42 GND GND PCIe RX2_P JX2_MGTRX0_P 43 U...

Page 32: ...F_IO_7_N FMC1 LA22_N 1V0 VCCINT 97 98 VCCINT 1V0 FMC1 LA24_P JX2_DIFF_IO_8_P 99 N26 P25 100 JX2_DIFF_IO_9_P FMC1 LA25_P FMC1 LA24_N JX2_DIFF_IO_8_N 101 N27 P26 102 JX2_DIFF_IO_9_N FMC1 LA25_N 1V0 VCCINT 103 104 2 5V 2V5 FMC1 LA28_P JX2_DIFF_IO_10_P 105 N28 T24 106 JX2_DIFF_ IO_11_P FMC1 LA27_P FMC1 LA28_N JX2_DIFF_IO_10_N 107 P28 T25 108 JX2_DIFF_ IO_11_N FMC1 LA27_N FMC_Vadj JX2_VCCIO_DIFF 109 11...

Page 33: ...e DDR voltage that is supplied to the DDR3 devices Since the Mini Module Plus Baseboard 2 supports the Virtex 5 Mini Module Plus the DDR voltage is selectable between 1 8 V DDR2 and 1 5 V 1 35 V DDR3 Since the Zynq utilizes DDR3 devices it is important to always have SW13 in the UP position marked K7 on the baseboard to insure the proper 1 5 V voltage is being supplied to the Zynq Mini Module s DD...

Page 34: ...q series devices These voltage settings can be modified by changing the position of the 0 ohm resistor s on the back side of the baseboard Refer the Mini Module plus Baseboard 2 User s Guide on the DRC for more detailed information about the baseboard power system www em avnet com en us design drc Pages Mini Module Plus Baseboard 2 aspx 2 11 Thermal Management An active heat sink is used to dissip...

Page 35: ...rated on the PCI Express bus using a PCI Express bus analyzer viewer such as PCI Tree NOTE The Mini Module Plus Baseboard does not get power from the PCI Express slot The external power supply shipped with the baseboard must be used to power the Zynq 7Z045 Mini Module Plus system 3 2 Micro SD Card Linux The supplied micro SD card shipped with the Zynq 7Z045 Mini Module Plus is pre programmed with ...

Page 36: ...Z045 Default DNP JP7 USB 2 0 VBUS SELECT Place this jumper when the USB 2 0 interface is to be used as the Host OTG This will provide VBUS with 5 0V to the endpoint device Default DNP JP8 PJTAG VREF Place this jumper to provide a 2 5 V reference voltage to a third party debugger Default DNP JP9 PFLASH WP Place this jumper to enable the Write Protect function for the parallel flash device U19 Defau...

Search results

Summary of Contents for Xilinx Zynq 7Z045

Reviews:

Related manuals for Xilinx Zynq 7Z045

Brands by name

Popular brands

Avnet Xilinx Zynq 7Z045, Manual

Search results

Summary of Contents for Xilinx Zynq 7Z045

Reviews:

Related manuals for Xilinx Zynq 7Z045

Brands by name

Popular brands