
MSC SM2S-IMX8M User Manual
49 / 92
5.2 Start-Up and Power-Down Behaviour
The module will behave in the following ways:
When coming from complete power off (5V unpowered), the module will boot if VIN_PWR_BAD# is high and 5V is present.
When OS is shut down and 5V is still powered, a power button press is required to restart the module.
If the module does not come up in test mode or force recovery mode it fetches the OS and the file system from the boot source, defined by the
BOOT_SEL strapping pins.
On pressing the Power button shorter than 8 seconds when powered, the module will initiate a shutdown and go off after ~5 seconds.
On keeping the Power button pressed for 8 seconds or longer, the module will shut down, and restart as soon as the Power button is
released.
5.3 Memory
5.3.1 SDRAM
The DDR Controller supports 32/16-bit LPDDR4-3200.
MSC SM2S-IMX8M
SMARC™ modules use one physical rank with up to 4GByte SDRAM.
Table 5-1: Available SDRAM options
CPU
Bus Width
Memory Size
Memory
Organisation
i.MX8M Dual, Quad and
QuadLite
64-bit Interface
1 GB
2x 32Mx16x8B
64-bit Interface
2 GB
4x 32Mx16x8B
64-bit Interface
4 GB
4x 64Mx16x8B
5.3.2 eMMC
Up to 64GB eMMC are supported. The eMMC is used in 8 bit interface mode.