manualshive.com logo in svg

Avnet SMARC MSC SM2S-IMX8M, User Manual, Page: 43 / 92

Share
Download
Avnet SMARC MSC SM2S-IMX8M User Manual Download Page 43

 

MSC SM2S-IMX8M User Manual 

 

 

 

 

 

 

 

43 / 92  

4.13 I²C Bus 

I2C_GP on the 

SMARC™ connector is also linked to an on-module EEPROM at address 0x50. 

For further I²C bus signals see also Camera, HDMI, LCD/LVDS and System Management interfaces. 

 

The I²C bus driven by CPU core function has the following key features: 

•

  Compatibility with I2C bus standard 

•

  Multimaster operation 

•

  Software programmability for one of 64 different serial clock frequencies 

•

  Software-selectable acknowledge bit 

•

  Interrupt-driven, byte-by-byte data transfer 

•

  Arbitration-lost interrupt with automatic mode switching from master to slave 

•

  Calling address identification interrupt 

•

  Start and stop signal generation/detection 

•

  Repeated Start signal generation 

•

  Acknowledge bit generation/detection 

•

  Bus-busy detection 

•

  Data rates up to 100kbits/s in Standard mode and 400kbits/s in Fast mode 

 

Table 4-13: I²C Signal Description 

Signal 

Pin Type 

Signal 
Level 

Pin on 
i.MX8M 

Pin name on 
i.MX8M 

Power 
Tolerance 

PU/PD 

Description 

I2C_GP_CK 

O OD 

1.8V CMOS 

G7 

I2C2_SCL 

1.8V 

PU 2.2k 1.8V 

General Purpose SMB clock output 

I2C_GP_DAT 

I/O OD 

1.8V CMOS 

F7 

I2C2_SDA 

1.8V 

PU 2.2k 1.8V 

General Purpose SMB data I/O line 

SMB_ALERT_1V8# 

I OD 

1.8V CMOS 

K19 

NAND_RE_B 

1.8V 

PU 2.2k 1.8V 

(CPU GPIO3_IO15) 

Summary of Contents for SMARC MSC SM2S-IMX8M

Page 1: ...SMARC Module MSC SM2S IMX8M SMARC Rev 2 0 Standard Version 1 1 18 03 2021 User Manual ...

Page 2: ... not an end user product It was developed and manufactured for further processing by trained personnel Disclaimer Although this document has been generated with the utmost care no warranty or liability for correctness or suitability for any particular purpose is implied The information in this document is provided as is and is subject to change without notice EMC Rules This unit has to be installe...

Page 3: ...roduct change notification and end of life management process assures early information of our customers Product Support MSC engineers and technicians are committed to provide support to our customers whenever needed Before contacting Technical Support of MSC Technologies GmbH please consult the respective pages on our web site at https www msc technologies eu support boards html for the latest do...

Page 4: ... 2 THERMAL SPECIFICATIONS 20 2 1 Thermal Definitions 20 3 MODULE CONNECTOR PINOUT 22 4 MODULE CONNECTOR SIGNAL DESCRIPTION 26 4 1 I S 27 4 2 Ethernet 28 4 3 PCI Express 29 4 4 USB 30 4 5 Camera 32 4 6 LVDS 34 4 7 HDMI DP 36 4 8 SPI Bus 37 4 9 CAN 38 4 10 GPIO 39 4 11 SDIO 40 4 12 UART 41 4 13 I C Bus 43 4 14 Watchdog 44 4 15 System Management 44 4 16 Boot Options 46 5 FUNCTIONS ON MODULE 48 5 1 CP...

Page 5: ...nning an Image 73 7 3 1 Booting SPL secondary program loader U Boot 73 7 3 2 Booting OS 76 7 3 3 Login to FS 82 7 3 4 SMARC GPIO access 83 7 3 5 Bug Reporting 84 7 3 6 Hotfixes and updating MSC LDK 89 8 TROUBLESHOOTING 90 8 1 Known issues and limitations 90 8 1 1 Issue 1 Thermal management for i MX 8M CPU 90 8 1 2 Issue 2 HDMI interface Some ACER monitors are not supported in 1080p mode 90 8 1 3 I...

Page 6: ... 7 10 Clone and enter the base MSC LDK repo 67 Figure 7 11 Create build directory 67 Figure 7 12 Enter build directory 68 Figure 7 13 Leave the MSC LDK container 68 Figure 7 14 Re start and re enter the MSC LDK container 69 Figure 7 15 Stop the MSC LDK container and release its resources 69 Figure 7 16 Building msc image base 71 Figure 7 17 Content of version_layer file 72 Figure 7 18 SPL boot sel...

Page 7: ...2 Table 4 6 LVDS Signal Description 34 Table 4 7 HDMI DP Signal Description 36 Table 4 8 SPI Signal Description 37 Table 4 9 CAN Signal Description 38 Table 4 10 GPIO Signal Description 39 Table 4 11 SDIO Signal Description 40 Table 4 12 UART Signal Description 41 Table 4 13 I C Signal Description 43 Table 4 14 Watchdog Signal Description 44 Table 4 15 System Management Signal Description 44 Table...

Page 8: ...MSC SM2S IMX8M User Manual 8 92 Revision History Rev Date Description 1 0 February 9th 2021 First Release 1 1 March 18 2021 Several fixes ...

Page 9: ...s of Application Processors IMX8MDQLQIEC pdf http www nxp com 5 Module Datasheet MSC SM2S IMX8M pdf https www msc technologies eu support boards smarc msc sm2s imx8m html 6 i MX Reference Manual i MX_Linux_Reference_Manual pdf Version L4 9 51_imx8mq ga 03 2018 http www nxp com 7 i MX Linux Reference Manual i MX_Reference_Manual pdf Version L4 14 98 2 0 0_ga 04 2019 http www nxp com 8 i MX Linux Us...

Page 10: ...04 2019 http www nxp com 10 i MX Yocto Project User s Guide i MX_Yocto_Project_User s_Guide pdf Version L4 14 98 2 0 0_ga 04 2019 http www nxp com 11 i MX Linux Release Notes i MX_Linux_Release_Notes pdf pdf Version L4 14 98 2 0 0_ga 05 2019 http www nxp com 12 Docker documentation https docs docker com ...

Page 11: ... connector Due to the standardized mechanics and interfaces the system can be scaled arbitrarily Despite the modular concept the system design is very flat and compact SMARC modules require a carrier board to build a working system For evaluation purposes MSC recommends the SMARC EP1 carrier board 1 1Key Features SoC NXP i MX 8M ARM CORTEX A53 Assembly options for i MX 8M Dual i MX 8M QuadLite and...

Page 12: ...100 1000BASE T Ethernet Optional HD Wireless Module SPB228 MU MIMO 2x2 with 802 11 ac a b g n and Bluetooth BLE support soldered on module USB 1x USB2 0 host port with device Interface capability and on the go OTG support Up to 2x USB2 0 host ports Up to 2x USB3 0 host ports SATA The i MX 8M does not support SATA GPIO 12x GPIO configurable as input or output push pull or open drain ...

Page 13: ...nterface I C bus for HDMI interface 2x I C bus for camera interfaces UART 2x legacy UARTs without RTS CTS support Up to 2x legacy UARTs with RTS CTS support NOTE Quantity of UART interfaces with RTS CTS support is dependent on SPI CAN mutual exclusive option SDIO eMMC SD Host Controller Standard Specification 3 0 and MMC System Specification 5 1 1bit 4bit SDIO eMMC NAND flash with up to 64GByte op...

Page 14: ...rovides a high accuracy RTC Optional RTC with temperature compensated DTCXO Watchdog Module provides a watchdog output to the SMARC connector Security Device Advanced Security Safety and Reliability integrated in the SOC Optional Infineon Trusted Platform Module TPM SLB9671 2 0 Environment Temperature 0 70 C all components commercial temp or better 40 85 C all components industrial temp 40 85 C st...

Page 15: ...MSC SM2S IMX8M User Manual 15 92 1 2 Block Diagram Figure 1 1 Block Diagram ...

Page 16: ...Ripple 20mV Current 1uA typical VDD 3V GND Power and signal return path All available GND connector pins shall be connected and tied to Carrier Board GND plane 1 4 Power Consumption 1 4 1 Use Cases Uboot Idle Ethernet link established HDMI monitor used no USB devices Linux Idle Ethernet link established HDMI monitor used no USB devices Linux Heavy Load CPU load 100 on each core memory tester HDMI ...

Page 17: ...3 at 1 3Ghz 2G LPDDR4 40 C to 85 C 73303 MSC SM2S IMX8M QC 13N0600I PCBFTX 8M Quad Quad Core Cortex A53 at 1 3Ghz 2G LPDDR4 40 C to 85 C 1 4 3 Measurement Results Table 1 3 Power Consumption Measurement Referece CPU Uboot Idle W Linux idle W Linux Heavy Load W MSC SM2S IMX8M DC 03N0600I PCBFTX 8M Dual Core Cortex A53 at 1 3Ghz 3 22 2 70 5 25 MSC SM2S IMX8M QC 13N0600I PCBFTX 8M Quad Quad Core Cort...

Page 18: ...ule Dimensions Figure 1 3 Overall Height without heat spreader of the SMARC Module The overall height is dependent on the selected MXM3 connector used on the baseboard Carrier PCB Module PCB 1 2mm BOT Side Component 1 3mm max TOP Side Component 3 0mm max 1 5mm min 5 7mm min ...

Page 19: ...of the SMARC module Production tolerance material deviation and thermal expansion lead to a range of possible pressure and bending No pressure with an air gap between the heat spreader and the chip case needs to be avoided and likewise too high a distortion Component types and their distance to the heat spreader mounting holes are considered Referring to data sheets of the relevant parts and AEC Q...

Page 20: ...l for the thermal design of a system is that each device on the module is operated within its specified thermal limits There may be system implementations where the heat spreader temperature could be higher In such a case the cooling solution design should be validated such that the thermal specifications of all the components on the module are not violated across the system operating temperature ...

Page 21: ...llowing table Table 2 1 Temperature Range Module Variant Tpcb_min Tpcb_max Module variants with commercial temperature components 0 C 70 C Module variants with extended temperature components 25 C 85 C Module variants with industrial temperature components 40 C 85 C Figure 2 1 Temperature measuring point on PCB Measuring point P ...

Page 22: ...I0_CK P9 GND S9 CSI0_CK P10 CSI1_RX1 S10 GND P11 CSI1_RX1 S11 CSI0_RX0 P12 GND S12 CSI0_RX0 P13 CSI1_RX2 S13 GND P14 CSI1_RX2 S14 CSI0_RX1 P15 GND S15 CSI0_RX1 P16 CSI1_RX3 S16 GND P17 CSI1_RX3 S17 NC Primary Top Side Secondary Bottom Side P18 GND S18 NC P19 GBE0_MDI3 S19 NC P20 GBE0_MDI3 S20 NC P21 GBE0_LINK100 S21 NC P22 GBE0_LINK1000 S22 NC P23 GBE0_MDI2 S23 NC P24 GBE0_MDI2 S24 NC P25 GBE0_LIN...

Page 23: ...P50 GND S50 I2S2_LRCK P51 NC S51 I2S2_SDOUT P52 NC S52 I2S2_SDIN P53 GND S53 I2S2_CK P54 SPI1_CS0 S54 NC P55 SPI1_CS1 S55 NC Primary Top Side Secondary Bottom Side P56 SPI1_CK S56 NC P57 SPI1_DO S57 NC P58 SPI1_DIN S58 NC P59 GND S59 NC P60 USB0 S60 NC P61 USB0 S61 GND P62 USB0_EN_OC S62 USB3_SSTx P63 USB0_VBUS_DET S63 USB3_SSTx P64 USB0_OTG_ID S64 GND P65 USB1 S65 USB3_SSRx P66 USB1 S66 USB3_SSRx...

Page 24: ...MI_D2 S94 DP0_LANE0 P94 GND S95 NC P95 HDMI_D1 S96 DP0_LANE1 Primary Top Side Secondary Bottom Side P96 HDMI_D1 S97 DP0_LANE1 P97 GND S98 DP0_HPD P98 HDMI_D0 S99 DP0_LANE2 P99 HDMI_D0 S100 DP0_LANE2 P100 GND S101 GND P101 HDMI_CK S102 DP0_LANE3 P102 HDMI_CK S103 DP0_LANE3 P103 GND S104 NC P104 HDMI_HPD S105 DP0_AUX P105 HDMI_CTRL_CK S106 DP0_AUX P106 HDMI_CTRL_DAT S107 LCD1_BKLT_EN P107 NC S108 LV...

Page 25: ...DS0_2 DSI0_D2 P132 SER0_CTS S133 LCD0_VDD_EN P133 GND S134 LVDS0_CK DSI0_CLK P134 SER1_TX S135 LVDS0_CK DSI0_CLK P135 SER1_RX S136 GND P136 SER2_TX S137 LVDS0_3 DSI0_D3 P137 SER2_RX S138 LVDS0_3 DSI0_D3 Primary Top Side Secondary Bottom Side P138 SER2_RTS S139 I2C_LCD_CK P139 SER2_CTS S140 I2C_LCD_DAT P140 SER3_TX S141 LCD0_BKLT_PWM P141 SER3_RX S142 NC P142 GND S143 GND P143 CAN0_TX S144 NC P144 ...

Page 26: ...sociated with the pin and for input and I O pins with the input voltage tolerance The pin power rail and the pin input voltage tolerance may be different Output pins are also classified as push pull PP or open drain OD The column PU PD describes additional schematic action taken on the module pull up resistor PU or pull down resistor PD ...

Page 27: ...MX8M Pin name on i MX8M Power Tolerance PU PD Description I2S0_LRCK O PP 1 8V CMOS H4 SAI2_TXFS 1 8V Sample synchronization signal to the codec s I2S0_CK O PP 1 8V CMOS J5 SAI2_TXC 1 8V Serial data clock I2S0_SDOUT O PP 1 8V CMOS G5 SAI2_TXD0 1 8V Serial TDM data output to the codec I2S0_SDIN I 1 8V CMOS H6 SAI2_RXD0 1 8V Serial TDM data inputs from the codec I2S2_LRCK O PP 1 8V CMOS G2 SAI3_TXFS ...

Page 28: ...MX8M Power Tolerance PU PD Description GBE0_MDI0 GBE0_MDI0 I O Analog n a n a 3 3V Media Dependent Interface Differential Pair 0 Used for the receive pair in 10 100 Mbit s mode GBE0_MDI1 GBE0_MDI1 I O Analog n a n a 3 3V Media Dependent Interface Differential Pair 1 Used for the transmit pair in 10 100 Mbit s mode GBE0_MDI2 GBE0_MDI2 I O Analog n a n a 3 3V Media Dependent Interface Differential P...

Page 29: ...xpress Reference Clock AC coupled on module Clock enabled by default Please contact support if spread spectrum support is required PCIE_B_TX PCIE_B_TX O LVDS PCIe E24 E25 PCIE2_TXN_P PCIE2_TXN_N According to PCIe spec PCI Express Differential Transmit Pairs AC coupled on module PCIE_B_RX PCIE_B_RX I LVDS PCIe D24 D25 PCIE2_RXN_P PCIE2_RXN_N According to PCIe spec PCI Express Differential Receive P...

Page 30: ...ding on the module variant different number of USB lanes are available Option 1 with USB 3 0 Hub USB 0 USB 2 0 host device OTG compliant USB 1 USB 2 0 host USB 2 3 USB 3 0 host USB 4 USB 2 0 host Option 2 without USB 3 0 Hub USB 0 USB 2 0 host device OTG compliant USB 1 USB 2 0 host Table 4 4 USB Signal Description Signal Option Availability Pin Type Signal Level Pin on i MX8M Pin name on i MX8M P...

Page 31: ...X USB 2 3 _SSRX 1 I USB n a n a 3 3V USB 3 0 receive signal differential pairs connected to USB hub USB0_VBUS_DET 1 2 I Analog D14 USB1_VBUS 5V external VBUS detection pin USB0_OTG_ID 1 2 I 3 3V CMOS M7 GPIO1_IO10 3 3V PU 10k 3 3V USB host client control select pin for the USB controller on the module USB0_EN_OC 1 2 I O OD 3 3V CMOS L7 K6 GPIO1_IO12 GPIO1_IO13 3 3V PU 10k 3 3V Host client dependen...

Page 32: ...lemented In case no USB power switches are used USB 0 4 _EN_OC pins may be left unconnected USB1 overcurrent detection and power enable function are not available in Option 2 USB1 power is always enabled in Option 2 4 5 Camera MIPI CSI 2 interface is supported on CSI0 with 2 lanes and on CSI1 with 4 lanes Table 4 5 HDMI Signal Description Signal Pin Type Signal Level Pin on i MX8M Pi name on i MX8...

Page 33: ... 8V CMOS M19 NAND_DATA06 1 8V PU 2 2k 1 8V CAM0 DDC clock line CPU GPIO3_IO13 I2C_CAM0_DAT I O OD 1 8V CMOS L19 NAND_DATA06 1 8V PU 2 2k 1 8V CAM0 DDC data line CPU GPIO3_IO12 I2C_CAM1_CK O OD 1 8V CMOS H1 SAI1_TXFS 1 8V PU 2 2k 1 8V CAM1 DDC clock line CPU GPIO4_IO10 I2C_CAM1_DAT I O OD 1 8V CMOS E1 SAI1_TXC 1 8V PU 2 2k 1 8V CAM1 DDC data line CPU GPIO4_IO11 CAM0_PWR I O OD 1 8V CMOS T6 GPIO1_IO...

Page 34: ...nal Level Pin on i MX8M Pin name on i MX8M Power Tolerance PU PD Description LVDS0_0 DSI0_D0 LVDS0_0 DSI0_D0 O LVDS n a n a 2 8V LVDS Channel 0 differential pair LVDS0_1 DSI0_D1 LVDS0_1 DSI0_D1 O LVDS n a n a 2 8V LVDS Channel 0 differential pair LVDS0_2 DSI0_D2 LVDS0_2 DSI0_D2 O LVDS n a n a 2 8V LVDS Channel 0 differential pair LVDS0_3 DSI0_D3 LVDS0_3 DSI0_D3 O LVDS n a n a 2 8V LVDS Channel 0 d...

Page 35: ...trol PWM3_OUT LCD1_VDD_EN O PP 1 8V CMOS J2 SAI1_RXD3 1 8V PD 10k LCD1 panel power enable CPU GPIO4_IO5 LCD1_BKLT_EN O PP 1 8V CMOS C1 SAI1_TXD7 1 8V LCD1 backlight enable CPU GPIO4_IO19 LCD1_BKLT_PWM O PP 1 8V CMOS G6 SPDIF_RX 1 8V PD 10k LCD1 backlight brightness control PWM2_OUT I2C_LCD_CK O PP 1 8V CMOS G8 I2C3_SCL 1 8V PU 2 2k 1 8V I C clock output for LVDS display use I2C3 I2C_LCD_DAT I O OD...

Page 36: ...V spec HDMI differential pair signals HDMI_CK HDMI_CK O CML 3 3V n a n a CML 3 3V spec HDMI differential clock HDMI_HPD I 3 3V CMOS W2 HDMI_HPD 5 5V PD 100k HDMI Hot Plug Detect HDMI_CTRL_CK O OD 1 8V CMOS R3 HDMI_DDC_SCL 1 8V PU 100k 1 8V HDMI DDC clock line HDMI_CTRL_DAT I O OD 1 8V CMOS P3 HDMI_DDC_SDA 1 8V PU 100k 1 8V HDMI DDC data line DP0_LANE 0 3 DP0_LANE 0 3 O CML 3 3V n a n a CML 3 3V sp...

Page 37: ...1 8V Master Input Slave Output SPI0_DO O PP 1 8V CMOS E5 ECSPI2_MOSI 1 8V Master Output Slave Input SPI0_CK O PP 1 8V CMOS C5 ECSPI2_SCLK 1 8V Clock Output SPI0_CS0 O PP 1 8V CMOS J22 NAND_DATA05 1 8V PU 10k 1 8V Chip Select0 available for baseboard usage GPIO3_IO11 SPI0_CS1 O PP 1 8V CMOS K1 SAI1_RXC 1 8V PU 10k 1 8V Chip Select1 available for baseboard usage GPIO4_IO01 SPI1_DIN I 1 8V CMOS B4 EC...

Page 38: ...Description Signal Pin Type Signal Level Pin on i MX8M Pin name on i MX8M Power Tolerance PU PD Description CAN0_TX O 1 8V CMOS n a n a 1 8V CAN0 Transmit output CAN1_TX O 1 8V CMOS n a n a 1 8V CAN1 Transmit output CAN0_RX I 1 8V CMOS n a n a 1 8V CAN0 Receive input CAN1_RX I 1 8V CMOS n a n a 1 8V CAN1 Receive input CAN0_INT I 1 8V CMOS H5 SAI2_MCLK 1 8V PU 10K 1 8V CAN0 multipurpose interrupt C...

Page 39: ...V CPU GPIO1_IO03 GPIO3 CAM1_RST I O 1 8V CMOS G21 NAND_CE1_B 1 8V PU 470K 1 8V CPU GPIO3_IO02 GPIO4 HDA_RST I O 1 8V CMOS P7 GPIO1_IO05 1 8V PU 470K 1 8V CPU GPIO1_IO05 GPIO5 PWM_OUT I O 1 8V CMOS T7 GPIO1_IO01 1 8V PU 470K 1 8V CPU GPIO1_IO01 PWM1_OUT GPIO6 TACHIN I O 1 8V CMOS N5 GPIO1_IO06 1 8V PU 470K 1 8V CPU GPIO1_IO06 GPIO7 I O 1 8V CMOS N6 GPIO1_IO07 1 8V PU 470K 1 8V CPU GPIO1_IO07 GPIO8 ...

Page 40: ...ta SDIO_D1 I O 3 3V 1V8 CMOS N21 SD2_DATA1 3 3V 1 8V PU 10k 3 3V 1 8V SDIO Controller Data SDIO_D2 I O 3 3V 1V8 CMOS P22 SD2_DATA2 3 3V 1 8V PU 10k 3 3V 1 8V SDIO Controller Data SDIO_D3 I O 3 3V 1V8 CMOS P21 SD2_DATA3 3 3V 1 8V PU 10k 3 3V 1 8V SDIO Controller Data SDIO_CMD I O 3 3V 1V8 CMOS M22 SD2_CMD 3 3V 1 8V PU 10k 3 3V 1 8V SDIO Controller Command SDIO_CK O 3 3V 1V8 CMOS L22 SD2_CLK 3 3V 1 ...

Page 41: ... driver direction control via CTS_B signal Edge selectable RTS_B and edge detect interrupts Status flags for various flow control and FIFO states Voting logic for improved noise immunity 16x oversampling Transmitter FIFO empty interrupt suppression UART internal clocks enable disable Auto baud rate detection up to 115 2 Kbit s Receiver and transmitter enable disable for power saving RX_DATA input ...

Page 42: ...ailable if SPI1 is implemented SER2_CTS I 1 8V CMOS D25 EIM_D23 1 8V PU 10k 1 8V UART handshake ready to send data See Note 2 below not available if SPI1 is implemented SER3_TX O 1 8V CMOS W5 KEY_COL0 1 8V PU 10k 1 8V UART transmit data See Note 2 below not available if SPI1 is implemented SER3_RX I 1 8V CMOS V6 KEQ_ROW0 1 8V PU 10k 1 8V UART receive data See Note 2 below not available if SPI1 is ...

Page 43: ...bitration lost interrupt with automatic mode switching from master to slave Calling address identification interrupt Start and stop signal generation detection Repeated Start signal generation Acknowledge bit generation detection Bus busy detection Data rates up to 100kbits s in Standard mode and 400kbits s in Fast mode Table 4 13 I C Signal Description Signal Pin Type Signal Level Pin on i MX8M P...

Page 44: ...t module by voltage divider CARRIER_PWR_ ON O PP 1 8V CMOS n a n a 1 8V Carrier board circuits should not be powered up until module asserts this signal CARRIER_STBY O PP 1 8V CMOS n a n a 1 8V Module asserts this signal to indicate standby power state RESET_OUT O PP 1 8V CMOS K4 SAI5_MCLK 1 8V PD 10k General purpose reset for carrier board CPU GPIO3_IO25 RESET_IN I OD 1 8V CMOS n a n a 1 8V PU 10...

Page 45: ...ay be sourced from user Sleep button or Carrier logic Carrier to float the line in in active state Driven by OD part on Carrier Pulled up on module CPU GPIO3_IO21 LID I OD 1 8V CMOS L4 SAI5_RXD1 1 8V PU 10k 1 8V Lid open close indication to Module Low indicates lid closure Carrier to float the line in in active state Active low level sensitive Pulled up on Module Driven by OD part on Carrier CPU G...

Page 46: ...S n a n a 1 8V PU 10k 1 8V Active low signal for test mode activation Pulled up on Module Driven by OD part on Carrier If the SMARC module is powered up with VIN_PWR_BAD left floating and RESET_IN left floating the module boots from selected boot device If FORCE_RECOV signal is pulled low at carrier the module boots via USB Client Mode this feature is only intended for recovery and requires dedica...

Page 47: ... at carrier the module boots from carrier SD Card directly Table 4 17 Boot Options BOOT_SEL2 BOOT_SEL1 BOOT_SEL0 Boot Source 0 GND GND GND Carrier SATA not supported 1 GND GND Float Carrier SD Card 2 GND Float GND Carrier eSPI with CS0 not supported 3 GND Float Float Carrier SPI with CS0 not supported 4 Float GND GND Module SD Card not supported 5 Float GND Float Remote boot LAN0 6 Float Float GND...

Page 48: ...U types Detailed information is provided in the module datasheet which can be downloaded from https www msc technologies eu support boards smarc msc sm2s imx8m html For details regarding the i MX8M CPU please refer to the NXP website see 4 For order information please contact Avnet Integrated MSC Figure 5 1 CPU Options ...

Page 49: ...ing the Power button shorter than 8 seconds when powered the module will initiate a shutdown and go off after 5 seconds On keeping the Power button pressed for 8 seconds or longer the module will shut down and restart as soon as the Power button is released 5 3 Memory 5 3 1 SDRAM The DDR Controller supports 32 16 bit LPDDR4 3200 MSC SM2S IMX8M SMARC modules use one physical rank with up to 4GByte ...

Page 50: ... 64G XI1 5 3 3 EEPROM 64Kb EEPROM for board data connected to I2C2 bus at address 0x50 NOTE The EEPROM on address 0x50 of the I2C_GP Bus holds the Board Information boardinfo structure which is evaluated by U Boot to determine the exact board variant and set necessary parameters Make sure to leave this EEPROM in place and DO NOT block address 0x50 on the I2C_GP Bus with other devices otherwise the...

Page 51: ...to the I2C4 bus at address 0x20 NOTE Current revision of the module integrates the Infineon TPM SLB9645 1 2 5 5 WiFi Module The i MX8M SMARC module offers an optional on board low power WiFi 2x2 MU MIMO and Bluetooth 5 0 The SPB228 provides up to 867Mbps data rate with 802 11ac on 80MHz channel and dual spatial streams The module is equipped with dual RF micro connectors U FL receptacles ...

Page 52: ... boot loader boot process has finished successfully Other usage options are possible Table 5 3 SW LED Signal Description Signal Pin Type Signal Level Pin on i MX8M Pin name on i MX8M Power Tolerance PU PD Description SW_LED I O 3 3V CMOS B3 SAI1_TXD6 3 3V Low active signal for LED control CPU GPIO4_IO18 The Power LED green colour is on if module power is completely ok The Reset LED red colour is o...

Page 53: ...e Debug connector are at 3 3V TTL level For using this Debug connector customers can obtain a small size debug board including FCC cable as an accessory with Order No 40402 This board converts the Debug UART signals to RS 232 level and offers them on a standard DSUB9 M connector Additionally this debug board has a soft reset button and three LEDs on GPIOs for additional debug capabilities Pinout 1...

Page 54: ...tor with 3 3V TTL level See also section 4 12 So for accessing the U Boot Linux console depending on availability and usage of the port on the target Carrier board either connection via the Carrier board SMARC connector or via the Debug connector on the module can be chosen to the same effect MSC Debug Adapter Order Part No 40402 Debug UART Adapter for i MX8 based SMARC Qseven and nanoRISC modules...

Page 55: ...Integrated MSC Technical Support if this feature is required Figure 5 5 Module top side with JTAG FFC connectors marked in red NOTE JTAG_MODE has an on module 10k pull down If JTAG Mode is left open or pulled low the CPU is in debug JTAG mode JTAG Interface is connected to the CPU core for software debug If pulled up JTAG is connected to the boundary scan chain of the CPU Pinout 1 Ground 2 RESET_I...

Page 56: ...de with MSC JTAG debug adapter MSC JTAG Adaptor FFC 10pol Order Part No 68948 Debug JTAG Adapter for i MX8 based SMARC modules with 10 pin FFC cable to connect COM module to connectors for JTAG connection to Lauterbach and or Goepel debuggers Use top top cables ...

Page 57: ... SMARC Connector 7 bit Address I2C1 I2C_PM I2C2 EEPROM I2C_GP 0x50 I2C3 I2C_LCD I2C4 TPM 0x20 PMIC1 0x30 PMIC2 0x31 Temp Sensor 0x71 RTC 0x32 PCIe Clock Generator 0x6B DSI to LVDS Bridge 0x2D GPIO based CAM0 GPIO based CAM1 HDMI HDMI_CTRL NOTE CAM0 and CAM1 are GPIO based bit banged Data transfer rates up to 100kbips are possible ...

Page 58: ...sed chip select CPU GPIO4_IO06 ECSPI2 CS0 A5 ECSPI2_SS0 CAN0 Controller Dedicated chip select for CAN0 Controller CS0 J22 NAND_DATA05 SPI0_CS0 GPIO based chip select CPU GPIO3_IO11 CS1 K1 SAI1_RXC SPI0_CS1 GPIO based chip select CPU GPIO4_IO01 QSPI_A CS0 H19 NAND_CE0_B QSPI NOR Flash Dedicated chip select for QSPI NOR Flash NOTE The dedicated chip select lines of ECSPI1 and ECSPI2 are reserved for...

Page 59: ...g the Linux kernel and the root filesystem Software that is part of a Linux image is called a package A package is generated from sources by a recipe which is a description of where to download the sources and how to compile them within Yocto A layer is a collection of recipes They are stackable and can extend or modify recipes defined in other layers A BSP provides the necessary layers to MSC LDK...

Page 60: ...ers may apply for specific Git repositories by sending an email with their public SSH key and desired project name to mailto support msc technologies eu Creating SSH key If there is no SSH key already available ssh id_rsa pub it can be generated with following command ssh keygen t rsa Example Figure 7 1 RSA key generation Share the public key in ssh id_rsa pub with MSC during Git registration ...

Page 61: ...ter the passphrase Trying to fetch repositories from the MSC Public GIT Server would fail with no hint that the passphrase is missing Configuring HTTP proxy Some source files will be downloaded from HTTP and FTP servers If a proxy must be used theseenvironment variables have to be set export http_proxy http my proxy 3128 export https_proxy http my proxy 3128 export ftp_proxy http my proxy 3128 Not...

Page 62: ... git02 msc ge com 9418 msc_ol99 msc ldk branch v1 5 0 msc ldk v 1 5 0 cd msc ldk v 1 5 0 Note The subsequent examples have been recorded with earlier release states of the BSP but the same methods and procedures still apply respectively Just the readings of v1 x x will change Example Figure 7 2 Clone base MSC LDK repo Your current directory now contains the following sub directories Figure 7 3 Ini...

Page 63: ...92 Example Figure 7 4 Create build directory Your current directory now looks like this Figure 7 5 Base directory content after setup build directory Step 3 Enter build directory To enter the build directory execute cd build 0102901 ...

Page 64: ...er versions of the host s OS such as Ubuntu 18 04 LTS or higher For detailed information about docker installation container handling and development under docker please take a look at 12 Step 1 Create MSC LDK container Execute git clone ssh gitolite msc git02 msc ge com 9418 msc_ol99 docker msc ldk cd docker msc ldk git checkout v1 5 0 cd docker msc ldk mkdir src mkdir p rootfs home ssh cp ssh id...

Page 65: ...MSC SM2S IMX8M User Manual 65 92 Example Figure 7 7 Create docker container for MSC LDK Part 1 ...

Page 66: ...t etc docker run privileged t i dns nmcli f IP4 DNS m multiline device show 2 1 sed rn s IP4 DNS 1 1 p name msc ldk h docker v pwd src src msc ldk bin bash Example Figure 7 9 Start and enter the MSC LDK container Step 3 Clone and enter the base MSC LDK repo Execute git clone ssh gitolite msc git02 msc ge com 9418 msc_ol99 msc ldk branch v1 5 0 msc ldk v 1 5 0 cd msc ldk v 1 5 0 ...

Page 67: ...er Manual 67 92 Example Note Example Screenshots still show v1 4 0 Figure 7 10 Clone and enter the base MSC LDK repo Step 4 Create build directory Execute setup sh bsp 0102901 Example Figure 7 11 Create build directory ...

Page 68: ... IMX8M User Manual 68 92 Step 5 Enter build directory Execute cd build 0102901 Example Figure 7 12 Enter build directory Leave the MSC LDK container Execute exit Example Figure 7 13 Leave the MSC LDK container ...

Page 69: ...ainer start msc ldk docker container exec ti msc ldk bin bash Example Figure 7 14 Re start and re enter the MSC LDK container Stop the MSC LDK container and release its resources Execute docker stop msc ldk docker rm msc ldk Example Figure 7 15 Stop the MSC LDK container and release its resources ...

Page 70: ...Wayland GUI and opensource Qt 5 image that fully supports the target device hardware Contains MSC features 2 0 GiB Yocto core images core image minimal A small image that only allows a device to boot 216 MiB core image base A console only image that fully supports the target device hardware 272 MiB Community images fsl image validation imx An i MX image with a GUI without any Qt content 1 7 GiB fs...

Page 71: ...MSC SM2S IMX8M User Manual 71 92 Example Figure 7 16 Building msc image base For more details and further information see also 10 Chapter 5 Image build ...

Page 72: ...e All generated images can be collected in a specific directory with user devhost msc ldk make install_images DESTDIR tmp msc ldk images Reproduce images with MSC LDK One of the key features of Yocto is the strong versioning of the resulting images Each package uses a predefined version e g busybox 1 32 0 When compiling an image yocto also prints the used GIT layer versions see Figure 7 16 Buildin...

Page 73: ...ries downloads and sstate cache can be moved or copied to improve build speed Time stamps in the image will be updated e g in etc issue 7 2 5 Image Deployment See 10 Chapter 6 Image Deployment Flashing an SD card image To flash an SD card image run the following command sudo dd if image name sdcard of dev sd partition bs 4MiB conv fsync 7 3 Running an Image 7 3 1 Booting SPL secondary program load...

Page 74: ...xample Figure 7 19 Forced SPL boot from carrier SD card Booting SPL U Boot from module eMMC flash The i MX 8M boot ROM code uses the module eMMC flash as primary and the carrier SD card as secondary fallback boot media The fall back media is always selected when booting from primary media is not possible empty corrupted etc ...

Page 75: ...M User Manual 75 92 Figure 7 20 SPL boot selector on EP1 carrier board S2801 eMMC flash boot mode default Example Figure 7 21 SPL boot from module eMMC flash Booting SPL from USB Not supported yet see section 8 1 3 ...

Page 76: ...chema Booting OS from carrier SD card In this configuration the Linux kernel image Image and the device tree blob are loaded from the first partition on the carrier SD card The second partition contains the Linux file system FS ext4 Figure 7 22 OS boot selector on EP1 carrier board S2802 Carrier SD card boot mode Example Figure 7 23 OS boot from carrier SD card ...

Page 77: ... kernel image Image and the device tree blob are loaded from the first partition on the module eMMC flash The second partition contains the Linux file system FS ext4 Figure 7 24 OS boot selector on EP1 carrier board S2802 Module eMMC flash boot mode Example Figure 7 25 OS boot from module eMMC flash ...

Page 78: ...ver on LAN Figure 7 26 OS boot selector on EP1 carrier board S2802 Network Ethernet boot mode Depending on your local network infrastructure set the following environment variables at the U Boot prompt setenv serverip TFTP NFS server IP setenv nfsroot nfs root path on NFS server saveenv Example Figure 7 27 Setting U Boot environment for net boot Then continue system boot with boot or simply reboot...

Page 79: ...MSC SM2S IMX8M User Manual 79 92 Example Figure 7 28 OS boot from network ...

Page 80: ... configuration the Linux kernel image Image and the device tree blob are being loaded from the first partition on the USB The second partition contains the Linux file system FS ext4 Figure 7 29 OS boot selector on EP1 carrier board S2802 USB boot mode Example Figure 7 30 OS boot from USB ...

Page 81: ...ad core HDMI up to 4K support msc sm2s imx8m qc 13N0600I lcdif lvds ama121a1 dtb i MX 8M quad core LVDS bridge and AMA121A1 1280x800 panel support msc sm2s imx8m qc 001 dp dts Develop i MX 8M q d core display port up to 4K support msc sm2s imx8m qc 001 dual head dts Develop i MX 8M q d core HDMI and LVDS bridge support msc sm2s imx8m qc 001 dual head single cam dts Develop i MX 8M q d core HDMI LV...

Page 82: ...ogin to FS Login is enabled via serial console 115200 baud 8 bits no parity All images also have telnet login enabled Table 7 3 Available user accounts Account Password Comment root mscldk Root user msc msc Standard user with sudo permissions ...

Page 83: ...able if CAM1 populated GPIO2 1 3 3 GPIO2 Not available if CAM0 populated GPIO3 3 2 66 GPIO3 Not available if CAM1 populated GPIO4 1 5 5 GPIO4 Available GPIO5 1 1 1 GPIO5 Available GPIO6 1 6 6 GPIO6 Available GPIO7 1 7 7 GPIO7 Available GPIO8 1 8 8 GPIO8 Available GPIO9 1 9 9 GPIO9 Available GPIO10 3 3 67 GPIO10 Available GPIO11 1 11 11 GPIO11 Available For detailed information about GPIO hardware ...

Page 84: ...rmation necessary for effectively responding to bug reports please use the msc_bug_report sh tool to generate bug report message It will collect all necessary information like hardware description configuration kernel logs etc Run msc_bug_report sh Figure 7 31 Bug report Main page ...

Page 85: ...MSC SM2S IMX8M User Manual 85 92 Select Edit User Message Figure 7 32 Bug report User message editor ...

Page 86: ...SC SM2S IMX8M User Manual 86 92 Enter bug report message and press Ctrl O and Ctrl X Optionally you can then view the message with the board report hardware information Figure 7 33 Bug report Viewer page ...

Page 87: ...SM2S IMX8M User Manual 87 92 Press Create a zip file and select the components you want to send e g bootlog mscio ini last kernel logs dmesg or the installed hardware Figure 7 34 Bug report Content selector ...

Page 88: ... ZIP to a disc and select the filesystem where to store the zip file It is recommended to use a USB stick Figure 7 35 Bug report Partition selector Send the files msc_bug_report_brief txt and msc_bug_report zip to MSC support msc technologies eu ...

Page 89: ...When MSC LDK is checked out the first time all hot fixes are applied automatically To update an older checkout and to pull all the newer hot fixes run scripts update py while in the MSC LDK root directory This will update MSC LDK and all layers Depending on the kind of hot fix running setup py again might also be necessary When a hot fix has been checked out explicitly running update will not make...

Page 90: ...rted in 1080p mode Source Hardware Software Workaround Solved with latest software release 8 1 3 Issue 4 USB 2 0 interface Not operable under U Boot Source Software Workaround Solved with latest software release 8 1 4 Issue 5 USB 3 0 interface Super speed not operable Source Hardware Software Solution Solved with latest software release 8 1 5 Issue 6 Temperature Management Unit TMU Sensors report ...

Page 91: ... latest hardware release 4th layout revision DV4 8 1 7 Issue 8 SDIO_PWR_EN signal is currently not supported in ROM code Source Hardware Solution Solved with latest hardware release 4th layout revision DV4 and latest software relase For further issues and limitations see also 11 Table 14 Known issues and workarounds for i MX 8M Family SoC ...

Page 92: ...M2S IMX8M User Manual 92 92 8 2 Support For additional help please contact MSC Technical Support Phone 49 8165 906 200 WWW https www msc technologies eu support boards html Email support msc technologies eu ...

Reviews:

No comments