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Avnet RFSoC, Getting Started Manual

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Avnet RFSoC Getting Started Manual Download Page 33

 
 

RFSoC Development Kit Getting Started Guide  

 

Page 33 

Appendix A:  Installation of USB UART Driver 

 

The Xilinx ZCU111 uses the Silicon Labs CP2102 USB-to-

UART Bridge IC.  This connects a PC’s USB port 

to the evaluation board and looks like a UART to the PC.  A virtual COM port will be created on the PC by 
means of a Silicon Labs CP2102 USB-to-UART bridge driver. Follow the instructions listed below to install 
the Silicon Labs drivers. 

Download and Install the Required Software 

1.  Using your web browser, navigate to the Silicon Labs website: 

 
 

http://www.silabs.com/products/mcu/pages/usbtouartbridgevcpdrivers.aspx

 

2.  Download the 

VCP Driver Kit

 

for your PC’s operating system.  Drivers for MacOS and Linux are also 

available. 

 

 

 

 

Summary of Contents for RFSoC

Page 1: ...ard Avnet makes no representation that this implementation is free from any claims of infringement You are responsible for obtaining any rights you may require for your implementation Avnet expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation including but not limited to any warranties or representations that this implementation is free from claims of infr...

Page 2: ...ng a CW Tone through the TX Path 14 Frequency Planning 15 Configuring the RF ADC in the DPD observation path 18 Configuring the RF DAC in the transmit path 23 Experiment 2 Generating an LTE signal through the TX Path 27 Appendix A Installation of USB UART Driver 33 Download and Install the Required Software 33 Determining the Virtual COM Port 35 Appendix III Getting Support 37 Avnet Support 37 Mat...

Page 3: ... other test equipment Avnet RFSoC Development Kit Overview The Avnet Zynq UltraScale RFSoC Development Kit with Qorvo RF Front End enables system architects to explore the entire signal chain from antenna to digital using tools from MathWorks and industry leading RF components from Qorvo We extend the functionality of the Xilinx Zynq UltraScale RFSoC ZCU111 Evaluation Kit by adding the Qorvo 2x2 S...

Page 4: ...for automated scripting and interface to MATLAB Requirements Laptop or PC with the following software installed MATLAB R2019b Free MATLAB Trial Package for Wireless Communications available i o DSP System Toolbox o Fixed Point Designer o Communications Toolbox o Communications Toolbox Support Package for Xilinx Zynq Based Radio o Signal Processing Toolbox o LTE Toolbox optional o 5G Toolbox option...

Page 5: ...B APPS tab without modifying your registry or other applications 1 From MATLAB Add Ons search for Avnet RFSoC Explorer and click install 2 From MATLAB Add Ons search for Communications Toolbox Support Package for Xilinx Zynq Based Radio and click install After installation choose Configure later if prompted ...

Page 6: ...the online ZCU111 Xilinx Wiki ZCU111 RFSoC RF Data Converter Evaluation Tool Getting Started Guide 1 Set the ZCU111 DIP switches SW6 as shown in the figure below which allows the ZCU111 board to boot from the SD card Figure 2 ZCU111 SD boot switch settings 2 Remove the SD card from the ZCU111 and insert into your PC Use an SD formatter tool to create a FAT partition https www sdcard org downloads ...

Page 7: ...in this document 5 Connect the Qorvo RF card ZCU111 antennae and cables as shown in Figure 6 Although no over the air transmission and reception is involved in this tutorial the antennae provide convenient 50 Ohm termination to the PA 1 6 Plug Ethernet and USB cables into your host PC 1 The Qorvo 2x2 Small Cell RF Front end 1 8GHz Card is designed for LTE Band 3 small cell applications in FDD mode...

Page 8: ...RFSoC Development Kit Getting Started Guide Page 8 Figure 6 Qorvo card mounted on ZCU111 Figure 7 Block diagram of Avnet RFSoC Development Kit ...

Page 9: ...output shown here Tera Term was used For information on setting up Tera Term to use with the ZCU111 USB UART port see Appendix A Installation of USB UART Driver later in this document 2 You should observe terminal output from U Boot and then Linux output appear in the Tera Term window After the final boot message Server Init Done press enter to generate a carriage return and command line prompt fr...

Page 10: ... the ifconfig command The ZCU111 Ethernet IP in this example is 192 168 0 105 Set a static IP for your host PC s Local Ethernet adapter Make sure your PC and the board are on the same subnet gateway etc Laptop Ethernet IP IP 192 168 0 106 Subnet 255 255 255 0 From the host PC open a Windows command prompt and ping the ZCU111 board to verify Ethernet connectivity C ping 192 168 0 105 ...

Page 11: ...opment Kit Getting Started Guide Page 11 From the host PC serial terminal connection to Linux running on the ZCU111 verify Ethernet connectivity by pinging your host PC root xilinx zcu111 2018_2 ping 192 168 0 106 ...

Page 12: ...via an SPI BUS Refer to the Avnet Qorvo 2x2 Small Cell RF Front end 1 8GHz Card Hardware User Guide for more information iii At the terminal command line type qorvo to launch the control menu for the Qorvo card Note If you make a mistake while typing commands in the Qorvo control menu use the keyboard Delete key to backspace at the command line Figure 8 Qorvo card command menu 2 Type v at the term...

Page 13: ...o card Type e at the terminal command line followed by a carriage return then type 1 to disable the TX TQL9092 driver amplifier Type d at the terminal command line followed by a carriage return then type 0 to disable the QPA9903 power amplifier With the digital attenuators at maximum attenuation the previous steps have ensured that no signal power is coupled back from the PA through the DPD observ...

Page 14: ...C This process repeats indefinitely constantly looping back to the start of the data in the memory buffer after reaching the end to generate a CW tone at the output of the DAC To avoid discontinuity between the start and end loop points of the CW tone RFSoC Explorer automatically adjusts the signal length to an integer number of cycles thereby ensuring a smooth zero crossing upon looping back to t...

Page 15: ...e host PC serial terminal connection to Linux running on the ZCU111 Frequency Planning Frequency planning involves selecting appropriate sampling rates Nyquist zone of operation and digital signal processing according to signal bandwidth I F frequency and board level filtering In this case the bandwidth of LTE band 3 is 75 MHz centered at 1842 MHz in the downlink While the bandwidth of the RF ADC ...

Page 16: ... LTE Band 3 signal we derive a suitable sampling rate at the RF ADC as shown below Figure 13 ADC sampling rate and decimation factor for LTE band 3 0 4 Fs_ADC D 75 2 MHz Solving for Fs_ADC and decimation factor D yields a suitable sampling rate for the RF ADC D 8 Fs_ADC 750 MHz 3 Ref Table 41 Decimation Filter Operating Modes Xilinx PG269 v2 1 May 22 2019 ...

Page 17: ...ng frequency Careful frequency planning can exploit this phenomenon to retrieve the signal of interest without need of a high sampling rate that is greater than the highest frequency component of the analog signal which in this case is 1843 MHz By purposely sampling at a lower rate to create aliasing copies of the signal can be made to appear at convenient frequency locations outside of the 1st Ny...

Page 18: ...card which connects to ADC07 Tile 3 Block 1 of the RFSoC device on ZCU111 1 Enable ADC Tile 3 in RFSoC Explorer Click to enter the tile Figure 15 RFSoC Explorer Enabling ADC Tile 3 2 Enable ADC23 This is the ADC block that connects to the channel 1 observation path of the Qorvo RF card Click OK on the warning box you will perform ADC calibration in a later step Figure 16 Enabling ADC23 in Tile 3 ...

Page 19: ...Hz for LTE Band 3 We wish to shift the CW tone at 1843 Mhz back to 1 MHz The complex mixer operates in the digital domain NCO frequency settings in the range of 10 GHz to 10 GHz translate to an effective NCO frequency in the digital domain from Fs 2 Fs 2 If the analog signal centered at Fc is in a higher Nyquist zone relative to the ADC sampling rate a digital alias will be shifted back to DC This...

Page 20: ...xplorer automatically calculates and displays Nyquist Zone and Calibration Mode as a function of the input signal center frequency Analog Fc and the ADC tile sampling rate Finally set decimation to 8X This will enable the cascade of 3 half band decimation filters within the RF ADC tile to attenuate unwanted frequency components above 67 MHz at baseband and reduce the sampling rate to 135 168 MSPS ...

Page 21: ...RFSoC Development Kit Getting Started Guide Page 21 Figure 19 Configuring the RF ADC ...

Page 22: ...he RF ADC block for the DPD observation path of the Qorvo RF card has been activated 6 We can now re enable the TX driver and PA of the Qorvo card Type d at the terminal command line followed by a carriage return then type 1 to enable the QPA9903 power amplifier in channel 1 of the Qorvo card Type e at the terminal command line followed by a carriage return then type 0 to enable the TX TQL9092 dri...

Page 23: ... Started Guide Page 23 Configuring the RF DAC in the transmit path 1 Enable DAC Tile 1 in RFSoC Explorer Click to enter the tile 2 Enable RF DAC block 2 connecting to channel 1 transmit path of the Qorvo RF card Refer to Figure 10 ...

Page 24: ...in the RF DAC tile to centre frequency of LTE Band 3 1842 MHz The resulting CW tone will be at 1843 MHz at the output of the DAC Set Interpolation 8 4 In the Signal Plot panel set to Frequency domain and select DAC Output This is useful for frequency planning by displaying the interpolated signal at the DAC output sampling rate post mixer Finally press Configure then Download to transfer the signa...

Page 25: ... end card The output of the power amplifier is coupled back through the DPD observation path towards the RF ADC for signal capture Figure 20 LTE Band 3 downlink and DPD observation signal paths 6 Return to the main tab and descend into ADC Tile 3 Select Single Capture and press Acquire 7 Observe the CW tone which has been mixed back to 1 MHz by the ADC mixer The signal level is low because the dig...

Page 26: ...nding increase in signal level which should ultimately reach approximately 1 65 dBFS Finally we can relax the Channel 1 TX digital attenuator which until now has remained at maximum attenuation 10 Type a at the terminal command line followed by a carriage return then enter the value 119 to decrease the attenuation by 1 65 dB The signal level should now be approximately 0 dBFS full scale Figure 21 ...

Page 27: ...al domain from the RFSoC Explorer graphical user interface GUI running under MATLAB on the host PC The digital signal data will be downloaded to the ZCU111 over TCP IP and stored in DDR4 memory dedicated to the RF DACs 1 Return to DAC Tile 1 From Signal Source of DAC 2 select Wireless Waveform From the Wireless Waveform Generator select LTE 4G Downlink RMC as the Waveform Type Figure 22 MathWorks ...

Page 28: ... Reference Channel Waveform Next use the Export dropdown menu in the top ribbon to select Export to RFSoC Explorer Figure 24 Export Waveform Generator Signal to RFSoC Explorer At the information dialog select Yes to maximize the signal level to the full available dynamic range for the DAC ...

Page 29: ...parameters table to confirm the new sampling rate of 798 720 MSPS Set interpolation factor to 8X Set the complex mixer frequency to 1842 MHz See Figure 20 Press Configure to send the DUC parameters to the RFSoC RF Data Converter subsystem Press Download to transfer the signal data from MATLAB to the DAC memory buffer of ZCU111 Figure 25 Generating a 20 MHz LTE waveform 4 Select Tile 3 ADCs within ...

Page 30: ...RFSoC Development Kit Getting Started Guide Page 30 5 The ADC23 settings should have retained the state from the previous experiment Press single capture ...

Page 31: ...e PA is causing non linear behavior as the amplifier approaches saturation Reduce the input level into the PA by typing a at the terminal command line followed by a carriage return then enter the value 127 to increase the attenuation and decrease the signal power entering the PA by 1 65 dB Press single capture to observe the PA now operating in the linear region This concludes experiment 2 ...

Page 32: ...ted usage of the Avnet RFSoC Explorer graphical user interface to control the ZCU111 development board generate and acquire signals through the Qorvo RF front end card in the MATLAB environment For a comprehensive description of the functionality of the RF front end see Qorvo 2x2 Small Cell RF Front end 1 8 GHz Card Hardware User Guide at www avnet com rfsockit ...

Page 33: ...rtual COM port will be created on the PC by means of a Silicon Labs CP2102 USB to UART bridge driver Follow the instructions listed below to install the Silicon Labs drivers Download and Install the Required Software 1 Using your web browser navigate to the Silicon Labs website http www silabs com products mcu pages usbtouartbridgevcpdrivers aspx 2 Download the VCP Driver Kit for your PC s operati...

Page 34: ...le is CP210x_VCP_Windows zip Once the archive is extracted open the folder where the archive was extracted and choose the correct installer for a 32 bit CP210xVCPInstaller_x86 exe or 64 bit CP210xVCPInstaller_x64 exe PC The installer will guide you through the setup Accept the license agreement and install the software on your PC Click Finish button when completed ...

Page 35: ...will pop up and enumeration of the driver will start Once finished a virtual COMx port is created and you are ready to setup a connection using Windows HyperTerminal or comparable serial terminal emulation utility Follow these instructions to determine the COMx port assigned to the USB to UART bridge 1 Open the Device Manager by right clicking on select Properties then click on the Device Manager ...

Page 36: ...ist You will see the Silicon Labs CP210x USB to UART Bridge and its assigned COM port In the example below it is COM4 Make note of this COM port number for use with the serial terminal you will use elsewhere in this design tutorial This concludes these USB UART driver and virtual COM port installation instructions ...

Page 37: ...r application or this tutorial please use the UltraScale RFSoC Forum on our element14 ZedBoard Community page https www element14 com zedboardcommunity To access the most current collateral visit the product page at www avnet com rfsockit MathWorks Support For questions regarding MathWorks software and support for the Avnet Zynq UltraScale RFSoC Development Kit please contact rfsoc mathworks com ...

Page 38: ...RFSoC Development Kit Getting Started Guide Page 38 Regulatory Compliance Information ...

Page 39: ...orm Generator in R2019b 18 Nov 2019 1 5 Updated waveform used in LTE Experiment 26 Nov 2019 1 6 Revised MATLAB SW Requirements Revised SD card preparation instruction i Free MATLAB Trial Package for Wireless Communications available here https www avnet com rfsockit iii Avnet Qorvo 2x2 Small Cell RF Front end 1 8GHz Card Hardware User Guide www avnet com rfsockit iv https www xilinx com support do...

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