Avnet PicoZed FMC V2, User Manual

Page: 22 / 42

22 22 Sept 2016
v1.1
2.10 Multi-Gigabit Transceivers (MGTs)
Four MGT interfaces are available with the 7015/30 SOMs:
1) LPC FMC – see section:
2.6
2) PCIe x1 – see section: 2.5
3) SFP+ - see section: 2.7
4) 4 SMAs – see section: 2.10.1
•
The PicoZed 7015 and 7030 SOMs have four multi-gigabit full-duplex transceiver lanes that
reside on Bank 112 of the Zynq device. These high speed transceivers are used to interface to
multiple high speed standard interfaces such as PCI Express and FMC. In addition to the PCIe
and FMC interface, they can interface the remaining available MGT pins to other high speed
interfaces such as Ethernet, Serial ATA, etc....
•
The PicoZed 7015 is fitted with the XC7Z015-1CLG485 and is enabled with GTP transceivers
which are capable of a transceiver data rate up to 3.75Gb/s. Speed grade devices of -2 or -3 are
capable of data transceiver rates up to 6.25Gb/s.
•
The PicoZed 7030 is fitted with the XC7Z030-1SBG485 and is enabled with GTX transceivers
which are capable of a transceiver data rate up to 6.6Gb/s. Speed grade devices of -2 or -3 are
also capable of data transceiver rates up to 6.6Gb/s in the SBG package.
Two differential MGT reference clock inputs are available for use with the GTP/GTX lanes. Either clock
input can be used as the clock reference for any one or more of the GT lanes in bank 112. This allows the
user to implement various protocols requiring different line rates.
Gigabit transceiver lanes and their associated reference clocks are connected to the carrier board via the
JX3 MicroHeader. The table below shows the MGT connections between the Zynq device and the JX
MicroHeader.
GTP/GTX
Name:
SOM Net Name:
Carrier Net
Name:
JX3 Pin:
MGT0
PCIE_TX0_P PCIE-TX0_P 13
PCIE_TX0_N PCIE-TX0_N 15
PCIE_RX0_P PCIE-RX0_P 8
PCIE_RX0_N PCIE-RX0_N 10
MGT1
MGTTX1_P MGTTX1_P 19
MGTTX1_N MGTTX1_N 21
MGTRX1_P MGTRX1_P 14
MGTRX1_N MGTRX1_N 16
MGT2
MGTTX2_P MGTTX2_P 25
MGTTX2_N MGTTX2_N 27
MGTRX2_P MGTRX2_P 20
MGTRX2_N MGTRX2_N 22
MGT3
FMC_MGT_TX_P FMC_MGT_TX_P 31
FMC_MGT_TX_N FMC_MGT_TX_N 33
FMC_MGT_RX_P FMC_MGT_RX_P 26
FMC_MGT_RX_N FMC_MGT_RX_N 28
MGT_REFCLK0
RSVD_PCIE_REFCLK0_P MGTREFCLK0_P 1
RSVD_PCIE_REFCLK0_N MGTREFCLK0_N 3
MGT_REFCLK1
RSVD_MGTREFCLK_P MGTREFCLK1_P 2
RSVD_MGTREFCLK_N MGTREFCLK1_N 4
Table 13 – MGT Pin Assignments