119
XMEGA B [DATASHEET]
8291B–AVR–01/2013
Figure 11-1. Interrupt controller overview.
11.4
Interrupts
All interrupts and the reset vector each have a separate program vector address in the program memory space. The
lowest address in the program memory space is the reset vector. All interrupts are assigned individual control bits for
enabling and setting the interrupt level, and this is set in the control registers for each peripheral that can generate
interrupts. Details on each interrupt are described in the peripheral where the interrupt is available.
All interrupts have an interrupt flag associated with it. When the interrupt condition is present, the interrupt flag will be set,
even if the corresponding interrupt is not enabled. For most interrupts, the interrupt flag is automatically cleared when
executing the interrupt vector. Writing a logical one to the interrupt flag will also clear the flag. Some interrupt flags are
not cleared when executing the interrupt vector, and some are cleared automatically when an associated register is
accessed (read or written). This is described for each individual interrupt flag.
If an interrupt condition occurs while another, higher priority interrupt is executing or pending, the interrupt flag will be set
and remembered until the interrupt has priority. If an interrupt condition occurs while the corresponding interrupt is not
enabled, the interrupt flag will be set and remembered until the interrupt is enabled or the flag is cleared by software.
Similarly, if one or more interrupt conditions occur while global interrupts are disabled, the corresponding interrupt flag
will be set and remembered until global interrupts are enabled. All pending interrupts are then executed according to their
order of priority.
Interrupts can be blocked when executing code from a locked section; e.g., when the boot lock bits are programmed.
This feature improves software security. Refer to
“Memory Programming” on page 377
for details on lock bit settings.
Interrupts are automatically disabled for up to four CPU clock cycles when the configuration change protection register is
written with the correct signature. Refer to
“Configuration Change Protection” on page 13
11.4.1 NMI – Non-Maskable Interrupts
Which interrupts represent NMI and which represent regular interrupts cannot be selected. Non-maskable interrupts
must be enabled before they can be used. Refer to the device datasheet for NMI present on each device.
An NMI will be executed regardless of the setting of the I bit, and it will never change the I bit. No other interrupts can
interrupt a NMI handler. If more than one NMI is requested at the same time, priority is static according to the interrupt
vector address, where the lowest address has highest priority.
11.4.2 Interrupt Response Time
The interrupt response time for all the enabled interrupts is three CPU clock cycles, minimum; one cycle to finish the
ongoing instruction and two cycles to store the program counter to the stack. After the program counter is pushed on the
stack, the program vector for the interrupt is executed. The jump to the interrupt handler takes three clock cycles.
Peripheral 1
Interrupt Controller
INT REQ
INT LEVEL
INT REQ
INT LEVEL
CPU INT REQ
CTRL
LEVEL Enable
CPU.SREG
Global
Interrupt
Enable
Priority
decoder
STATUS
INTPRI
INT ACK
INT ACK
Peripheral n
INT LEVEL
INT REQ
INT ACK
CPU
CPU INT ACK
CPU ”RETI”
Sleep
Controller
Wake-up
Summary of Contents for XMEGA B
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