Atmel SAM9X25, Manual

Page: 469 / 1145

469
11054A–ATARM–27-Jul-11
SAM9X25
469
11054A–ATARM–27-Jul-11
SAM9X25
31. DMA Controller (DMAC)
31.1 Description
The DMA Controller (DMAC) is an AHB-central DMA controller core that transfers data from a
source peripheral to a destination peripheral over one or more AMBA buses. One channel is
required for each source/destination pair. In the most basic configuration, the DMAC has one
master interface and one channel. The master interface reads the data from a source and writes
it to a destination. Two AMBA transfers are required for each DMAC data transfer. This is also
known as a dual-access transfer.
The DMAC is programmed via the APB interface.
The DMAC embeds 8 channels:
31.2 Embedded Characteristics
• Two DMACs
• DMAC0 is full featured and optimized for memory-to-memory transfers thanks to the 64-word
FIFO on channel 0
• DMAC1 is optimized for peripheral-to-memory transfers, without PIP support
• Acting as Two Matrix Masters
• Embeds 8 unidirectional channels with programmable priority
• Address Generation
– Source/Destination address programming
– Address increment, decrement or no change
– DMA chaining support for multiple non-contiguous data blocks through use of linked
lists
– Scatter support for placing fields into a system memory area from a contiguous
transfer. Writing a stream of data into non-contiguous fields in system memory
– Gather support for extracting fields from a system memory area into a contiguous
transfer
– User enabled auto-reloading of source, destination and control registers from initially
programmed values at the end of a block transfer
– Auto-loading of source, destination and control registers from system memory at end
of block transfer in block chaining mode
DMAC Channel Number FIFO Size
0 64
1 16
2 16
3 16
4 16
5 16
6 16
7 16