Atmel SAM9X25, Manual

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SAM9X25
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SAM9X25
22.4 Block Diagram
Figure 22-2. General Clock Block Diagram
22.5 Processor Clock Controller
The PMC features a Processor Clock Controller (PCK) that implements the Processor Idle
Mode. The Processor Clock can be disabled by writing the System Clock Disable Register
(PMC_SCDR). The status of this clock (at least for debug purposes) can be read in the System
Clock Status Register (PMC_SCSR).
The Processor Clock PCK is enabled after a reset and is automatically re-enabled by any
enabled interrupt. The Processor Idle Mode is achieved by disabling the Processor Clock and
entering Wait for Interrupt Mode. The Processor Clock is automatically re-enabled by any
enabled fast or normal interrupt, or by the reset of the product.
Note: The ARM Wait for Interrupt mode is entered by means of CP15 coprocessor operation. Refer to
the Atmel application note, Optimizing Power Consumption for AT91SAM9261-based Systems,
http://www.atmel.com/dyn/resources/prod_documents/doc6217.pdf .
When the Processor Clock is disabled, the current instruction is finished before the clock is
stopped, but this does not prevent data transfers from other masters of the system bus.
UHP4 8 M
UHP12M
MCK
int
PCK
/1 /2 / 3 /4
pck[..]
ON/OFF
/1,/2
U S B
OHCI
U S BDIV+1
/4
U S B
EHCI
U S B S
Divider
X /1 /1.5 /2
Divider
PLLACK
UPLLCK
UPLLCK
S LCK
MAINCK
S LCK
MAINCK
M as ter Clock Controller
S y s Clk DDR
Progr a mm ab le Clock Controller
Periph_clk[..]
Pre s c a ler
/1,/2,/4,...,/64
Pre s c a ler
/1,/2,/4,...,/64
Peripher a l s
Clock Controller
ON/OFF
Proce ss or
Clock
Controller