Atmel SAM9X25, Manual

Page: 169 / 1145

169
11054A–ATARM–27-Jul-11
SAM9X25
169
11054A–ATARM–27-Jul-11
SAM9X25
21. Clock Generator (CKGR)
21.1 Description
The Clock Generator User Interface is embedded within the Power Management Controller and
is described in
Section 22.13 ”Power Management Controller (PMC) User Interface” . However,
the Clock Generator registers are named CKGR_.
21.2 Embedded Characteristics
The Clock Generator is made up of:
• A Low Power 32,768 Hz Slow Clock Oscillator with bypass mode
• A Low Power RC Oscillator
• A 3 to 20 MHz Crystal Oscillator, which can be bypassed (12 MHz needed in case of USB)
• A Fast RC Oscillator, at 12 MHz.
• A 480 MHz UTMI PLL providing a clock for the USB High Speed Device Controller
• A 400 to 800 MHz programmable PLL (input from 8 to 16 MHz), capable of providing the
clock MCK to the processor and to the peripherals.
It provides the following clocks:
• SLCK, the Slow Clock, which is the only permanent clock within the system
• MAINCK is the output of the Main Clock Oscillator selection: either Crystal Oscillator or 12
MHz Fast RC Oscillator
• PLLACK is the output of the Divider and 400 to 800 MHz programmable PLL (PLLA)
• UPLLCK is the output of the 480 MHz UTMI PLL (UPLL)