840
11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
35.7.4
TC Stepper Motor Mode Register
Name:
TC_SMMRx [x=0..2]
Address:
0x40010008 (0)[0], 0x40010048 (0)[1], 0x40010088 (0)[2], 0x40014008 (1)[0], 0x40014048 (1)[1],
0x40014088 (1)[2]
Access:
Read-write
This register can only be written if the WPEN bit is cleared in
“TC Write Protect Mode Register” on page 858
• GCEN: Gray Count Enable
0 = TIOAx [x=0..2] and TIOBx [x=0..2] are driven by internal counter of channel x.
1 = TIOAx [x=0..2] and TIOBx [x=0..2] are driven by a 2-bit gray counter.
• DOWN: DOWN Count
0 = Up counter.
1 = Down counter.
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
DOWN
GCEN
Summary of Contents for SAM4S Series
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Page 1143: ...1143 11100B ATARM 31 Jul 12 SAM4S Series Preliminary Figure 43 4 64 lead LQFP Package Drawing ...
Page 1145: ...1145 11100B ATARM 31 Jul 12 SAM4S Series Preliminary Figure 43 5 64 lead QFN Package Drawing ...